Commit c4098885 authored by Frank Li's avatar Frank Li Committed by Shawn Guo
Browse files

arm64: dts: imx8dxl: add lpspi support 



Add lpspi0 lpspi1 lpspi2 lpspi3 node at common dma subsystem.
Change irq number for 8dxl.

Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 86d1625d

arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi

+112 −0
Original line number Diff line number Diff line
@@ -20,6 +20,70 @@ dma_subsys: bus@5a000000 { 
		clock-output-names = "dma_ipg_clk";

	};



	lpspi0: spi@5a000000 {

		compatible = "fsl,imx7ulp-spi";

		reg = <0x5a000000 0x10000>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		clocks = <&spi0_lpcg 0>,

			 <&spi0_lpcg 1>;

		clock-names = "per", "ipg";

		assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <20000000>;

		power-domains = <&pd IMX_SC_R_SPI_0>;

		status = "disabled";

	};



	lpspi1: spi@5a010000 {

		compatible = "fsl,imx7ulp-spi";

		reg = <0x5a010000 0x10000>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		clocks = <&spi1_lpcg 0>,

			 <&spi1_lpcg 1>;

		clock-names = "per", "ipg";

		assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <60000000>;

		power-domains = <&pd IMX_SC_R_SPI_1>;

		status = "disabled";

	};



	lpspi2: spi@5a020000 {

		compatible = "fsl,imx7ulp-spi";

		reg = <0x5a020000 0x10000>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		clocks = <&spi2_lpcg 0>,

			 <&spi2_lpcg 1>;

		clock-names = "per", "ipg";

		assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <60000000>;

		power-domains = <&pd IMX_SC_R_SPI_2>;

		status = "disabled";

	};



	lpspi3: spi@5a030000 {

		compatible = "fsl,imx7ulp-spi";

		reg = <0x5a030000 0x10000>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		clocks = <&spi3_lpcg 0>,

			 <&spi3_lpcg 1>;

		clock-names = "per", "ipg";

		assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <60000000>;

		power-domains = <&pd IMX_SC_R_SPI_3>;

		status = "disabled";

	};



	lpuart0: serial@5a060000 {

		reg = <0x5a060000 0x1000>;

		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
@@ -60,6 +124,54 @@ dma_subsys: bus@5a000000 { 
		status = "disabled";

	};



	spi0_lpcg: clock-controller@5a400000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5a400000 0x10000>;

		#clock-cells = <1>;

		clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,

			 <&dma_ipg_clk>;

		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;

		clock-output-names = "spi0_lpcg_clk",

				     "spi0_lpcg_ipg_clk";

		power-domains = <&pd IMX_SC_R_SPI_0>;

	};



	spi1_lpcg: clock-controller@5a410000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5a410000 0x10000>;

		#clock-cells = <1>;

		clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,

			 <&dma_ipg_clk>;

		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;

		clock-output-names = "spi1_lpcg_clk",

				     "spi1_lpcg_ipg_clk";

		power-domains = <&pd IMX_SC_R_SPI_1>;

	};



	spi2_lpcg: clock-controller@5a420000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5a420000 0x10000>;

		#clock-cells = <1>;

		clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,

			 <&dma_ipg_clk>;

		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;

		clock-output-names = "spi2_lpcg_clk",

				     "spi2_lpcg_ipg_clk";

		power-domains = <&pd IMX_SC_R_SPI_2>;

	};



	spi3_lpcg: clock-controller@5a430000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5a430000 0x10000>;

		#clock-cells = <1>;

		clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,

			 <&dma_ipg_clk>;

		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;

		clock-output-names = "spi3_lpcg_clk",

				     "spi3_lpcg_ipg_clk";

		power-domains = <&pd IMX_SC_R_SPI_3>;

	};



	uart0_lpcg: clock-controller@5a460000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x5a460000 0x10000>;

arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -54,3 +54,19 @@ 
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

	interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;

};



&lpspi0 {

	interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;

};



&lpspi1 {

	interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;

};



&lpspi2 {

	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;

};



&lpspi3 {

	interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

};