Commit c3ee3a9e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2022-02-11' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular fixes pull, mostly i915 and amd fixes, along with a
  maintainers update for fbdev core.

  Otherwise just some build fixes and vc4 HDMI fixes.

  fbdev:
   - MAINTAINERS: add Daniel as fbdev core module maintainer
   - build warning fix
   - implicit type cast fix

  panel:
   - simple: Fix assignments from panel_dpi_probe()

  privacy-screen:
   - fix docs warning

  i915:
   - non-x86 build fix
   - ttm error propogation fix
   - drrs on hsw/ivb disabled
   - BIOS readout fixes
   - missing stackdepot oops fix

  amd:
   - DCN 3.1 display fixes
   - GC 10.3.1 harvest fix
   - Page flip irq fix
   - hwmon label fix
   - DCN 2.0 display fix

  rockchip:
   - fix HDMI error cleanup
   - fix RK3399 VOP register fields

  vc4:
   - HDMI fixes
   - remove redundant code"

* tag 'drm-fixes-2022-02-11' of git://anongit.freedesktop.org/drm/drm: (25 commits)
  drm/amdgpu/display: change pipe policy for DCN 2.0
  drm/amd/pm: fix hwmon node of power1_label create issue
  drm/amd/display: keep eDP Vdd on when eDP stream is already enabled
  drm/amd/display: fix yellow carp wm clamping
  drm/amd/display: Cap pflip irqs per max otg number
  drm/amdgpu: add utcl2_harvest to gc 10.3.1
  display/amd: decrease message verbosity about watermarks table failure
  drm/rockchip: vop: Correct RK3399 VOP register fields
  drm/rockchip: dw_hdmi: Do not leave clock enabled in error case
  MAINTAINERS: Add entry for fbdev core
  fbcon: Avoid 'cap' set but not used warning
  drm/privacy-screen: Fix sphinx warning
  drm/i915: Workaround broken BIOS DBUF configuration on TGL/RKL
  drm/i915: Populate pipe dbuf slices more accurately during readout
  drm/i915: Allow !join_mbus cases for adlp+ dbuf configuration
  drm/i915: Fix header test for !CONFIG_X86
  drm/i915/ttm: Return some errors instead of trying memcpy move
  drm/i915: Disable DRRS on IVB/HSW port != A
  drm/i915: Fix oops due to missing stack depot
  drm/vc4: crtc: Fix redundant variable assignment
  ...
parents 32f6c5d0 95e875bd

MAINTAINERS

+6 −0
Original line number Diff line number Diff line
@@ -7575,6 +7575,12 @@ S: Maintained 
W:	http://floatingpoint.sourceforge.net/emulator/index.html

F:	arch/x86/math-emu/









FRAMEBUFFER CORE









M:	Daniel Vetter <daniel@ffwll.ch>









F:	drivers/video/fbdev/core/









S:	Odd Fixes









T:	git git://anongit.freedesktop.org/drm/drm-misc

















FRAMEBUFFER LAYER









M:	Helge Deller <deller@gmx.de>









L:	linux-fbdev@vger.kernel.org
































drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c



+6
−1






























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Diff line







@@ -543,7 +543,9 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)







		adev->gfx.config.max_sh_per_se *









		adev->gfx.config.max_shader_engines);



















	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) {









	switch (adev->ip_versions[GC_HWIP][0]) {









	case IP_VERSION(10, 3, 1):









	case IP_VERSION(10, 3, 3):









		/* Get SA disabled bitmap from eFuse setting */









		efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);









		efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;








@@ -566,6 +568,9 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)







		disabled_sa = tmp;



















		WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa);









		break;









	default:









		break;









	}









}










































drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c



+1
−1






























Original line number
Diff line number
Diff line







@@ -3653,7 +3653,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)

















	/* Use GRPH_PFLIP interrupt */









	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;









			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;









			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;









			i++) {









		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);









		if (r) {
































drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c



+5
−1






























Original line number
Diff line number
Diff line







@@ -120,6 +120,10 @@ static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,







	result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);



















	if (result == VBIOSSMC_Result_Failed) {









		if (msg_id == VBIOSSMC_MSG_TransferTableDram2Smu &&









		    param == TABLE_WATERMARKS)









			DC_LOG_WARNING("Watermarks table not configured properly by SMU");









		else









			ASSERT(0);









		REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);









		return -1;
































drivers/gpu/drm/amd/display/dc/core/dc.c



+2
−0






























Original line number
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Diff line







@@ -1220,6 +1220,8 @@ struct dc *dc_create(const struct dc_init_data *init_params)

















		dc->caps.max_dp_protocol_version = DP_VERSION_1_4;



















		dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;



















		if (dc->res_pool->dmcu != NULL)









			dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;









	}