Unverified Commit c3ecca33 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!4347 【OLK-6.6】AMD: CXL RCH Protocol Error Handling supporting 

Merge Pull Request from: @kile2009 
 
backporting the patches from upstream,
https://lore.kernel.org/all/20231018171713.1883517-1-rrichter@amd.com/

issue:
https://gitee.com/openeuler/kernel/issues/I8ZZ5K 
 
Link:https://gitee.com/openeuler/kernel/pulls/4347

 

Reviewed-by: default avatarLiu Chao <liuchao173@huawei.com>
Reviewed-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents fc0bee18 a36ebbd6

arch/arm64/configs/openeuler_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -1934,6 +1934,7 @@ CONFIG_PCIEPORTBUS=y 
CONFIG_HOTPLUG_PCI_PCIE=y

CONFIG_PCIEAER=y

CONFIG_PCIEAER_INJECT=m

CONFIG_PCIEAER_CXL=y

CONFIG_PCIE_ECRC=y

CONFIG_PCIEASPM=y

CONFIG_PCIEASPM_DEFAULT=y

arch/x86/configs/openeuler_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -1986,6 +1986,7 @@ CONFIG_PCIEPORTBUS=y 
CONFIG_HOTPLUG_PCI_PCIE=y

CONFIG_PCIEAER=y

CONFIG_PCIEAER_INJECT=m

CONFIG_PCIEAER_CXL=y

CONFIG_PCIE_ECRC=y

CONFIG_PCIEASPM=y

CONFIG_PCIEASPM_DEFAULT=y

drivers/cxl/core/core.h

+1 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ struct cxl_rcrb_info; 
resource_size_t __rcrb_to_component(struct device *dev,

				    struct cxl_rcrb_info *ri,

				    enum cxl_rcrb which);

u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);



extern struct rw_semaphore cxl_dpa_rwsem;

extern struct rw_semaphore cxl_region_rwsem;

drivers/cxl/core/hdm.c

+19 −29
Original line number Diff line number Diff line
@@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm) 
		cxlhdm->interleave_mask |= GENMASK(14, 12);

}



static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,

				struct cxl_component_regs *regs)

{

	struct cxl_register_map map = {

		.host = &port->dev,

		.resource = port->component_reg_phys,

		.base = crb,

		.max_size = CXL_COMPONENT_REG_BLOCK_SIZE,

	};



	cxl_probe_component_regs(&port->dev, crb, &map.component_map);

	if (!map.component_map.hdm_decoder.valid) {

		dev_dbg(&port->dev, "HDM decoder registers not implemented\n");

		/* unique error code to indicate no HDM decoder capability */

		return -ENODEV;

	}



	return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));

}



static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)

{

	struct cxl_hdm *cxlhdm;
@@ -153,9 +133,9 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info) 
struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,

				   struct cxl_endpoint_dvsec_info *info)

{

	struct cxl_register_map *reg_map = &port->reg_map;

	struct device *dev = &port->dev;

	struct cxl_hdm *cxlhdm;

	void __iomem *crb;

	int rc;



	cxlhdm = devm_kzalloc(dev, sizeof(*cxlhdm), GFP_KERNEL);
@@ -164,19 +144,29 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 
	cxlhdm->port = port;

	dev_set_drvdata(dev, cxlhdm);



	crb = ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);

	if (!crb && info && info->mem_enabled) {

		cxlhdm->decoder_count = info->ranges;

		return cxlhdm;

	} else if (!crb) {

	/* Memory devices can configure device HDM using DVSEC range regs. */

	if (reg_map->resource == CXL_RESOURCE_NONE) {

		if (!info || !info->mem_enabled) {

			dev_err(dev, "No component registers mapped\n");

			return ERR_PTR(-ENXIO);

		}



	rc = map_hdm_decoder_regs(port, crb, &cxlhdm->regs);

	iounmap(crb);

	if (rc)

		cxlhdm->decoder_count = info->ranges;

		return cxlhdm;

	}



	if (!reg_map->component_map.hdm_decoder.valid) {

		dev_dbg(&port->dev, "HDM decoder registers not implemented\n");

		/* unique error code to indicate no HDM decoder capability */

		return ERR_PTR(-ENODEV);

	}



	rc = cxl_map_component_regs(reg_map, &cxlhdm->regs,

				    BIT(CXL_CM_CAP_CAP_ID_HDM));

	if (rc) {

		dev_err(dev, "Failed to map HDM capability.\n");

		return ERR_PTR(rc);

	}



	parse_hdm_decoder_caps(cxlhdm);

	if (cxlhdm->decoder_count == 0) {

drivers/cxl/core/mbox.c

+2 −0
Original line number Diff line number Diff line
@@ -1402,6 +1402,8 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev) 
	mutex_init(&mds->mbox_mutex);

	mutex_init(&mds->event.log_lock);

	mds->cxlds.dev = dev;

	mds->cxlds.reg_map.host = dev;

	mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;

	mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;



	return mds;