Commit c3bd49cd authored Oct 06, 2022 by John Harrison

drm/i915: Fix compute pre-emption w/a to apply to compute engines



An earlier patch added support for compute engines. However, it missed
enabling the anti-pre-emption w/a for the new engine class. So move
the 'compute capable' flag earlier and use it for the pre-emption w/a
test.

Fixes: c674c5b9 ("drm/i915/xehp: CCS should use RCS setup functions")
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: "Michał Winiarski" <michal.winiarski@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221006213813.1563435-3-John.C.Harrison@Intel.com

parent 568944af

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+12 −12

Original line number	Diff line number	Diff line
		@@ -486,6 +486,17 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
		engine->logical_mask = BIT(logical_instance);
		__sprint_engine_name(engine);

		if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
		__ffs(CCS_MASK(engine->gt)) == engine->instance) \|\|
		engine->class == RENDER_CLASS)
		engine->flags \|= I915_ENGINE_FIRST_RENDER_COMPUTE;

		/* features common between engines sharing EUs */
		if (engine->class == RENDER_CLASS \|\| engine->class == COMPUTE_CLASS) {
		engine->flags \|= I915_ENGINE_HAS_RCS_REG_STATE;
		engine->flags \|= I915_ENGINE_HAS_EU_PRIORITY;
		}

		engine->props.heartbeat_interval_ms =
		CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
		engine->props.max_busywait_duration_ns =
		@@ -498,20 +509,9 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
		CONFIG_DRM_I915_TIMESLICE_DURATION;

		/* Override to uninterruptible for OpenCL workloads. */
		if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
		if (GRAPHICS_VER(i915) == 12 && (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
		engine->props.preempt_timeout_ms = 0;

		if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
		__ffs(CCS_MASK(engine->gt)) == engine->instance) \|\|
		engine->class == RENDER_CLASS)
		engine->flags \|= I915_ENGINE_FIRST_RENDER_COMPUTE;

		/* features common between engines sharing EUs */
		if (engine->class == RENDER_CLASS \|\| engine->class == COMPUTE_CLASS) {
		engine->flags \|= I915_ENGINE_HAS_RCS_REG_STATE;
		engine->flags \|= I915_ENGINE_HAS_EU_PRIORITY;
		}

		/* Cap properties according to any system limits */
		#define CLAMP_PROP(field) \
		do { \