Commit c39830a4 authored by Sunil Goutham's avatar Sunil Goutham Committed by David S. Miller
Browse files

octeontx2-pf: cn10k: Config DWRR weight based on MTU 



Program SQ, MDQ, TL4 to TL2 transmit scheduler queues' DWRR
weight based on DWRR MTU programmed at NIX_AF_DWRR_RPM_MTU.
The DWRR MTU from admin function is retrieved via mbox.

On OcteaonTx2 silicon, admin function driver responds with DWRR
MTU as '1'. This helps to avoid silicon specific transmit
scheduler DWRR quantum/weight configuration logic.

Signed-off-by: default avatarSunil Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 76660df2

drivers/net/ethernet/marvell/octeontx2/af/common.h

+0 −4
Original line number Diff line number Diff line
@@ -146,10 +146,6 @@ enum nix_scheduler { 
#define TXSCH_RR_QTM_MAX		((1 << 24) - 1)

#define TXSCH_TL1_DFLT_RR_QTM		TXSCH_RR_QTM_MAX

#define TXSCH_TL1_DFLT_RR_PRIO		(0x1ull)

#define MAX_SCHED_WEIGHT		0xFF

#define DFLT_RR_WEIGHT			71

#define DFLT_RR_QTM	((DFLT_RR_WEIGHT * TXSCH_RR_QTM_MAX) \

			 / MAX_SCHED_WEIGHT)

#define CN10K_MAX_DWRR_WEIGHT          16384 /* Weight is 14bit on CN10K */



/* Min/Max packet sizes, excluding FCS */

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+4 −0
Original line number Diff line number Diff line
@@ -1032,8 +1032,12 @@ struct nix_bp_cfg_rsp { 


struct nix_hw_info {

	struct mbox_msghdr hdr;

	u16 rsvs16;

	u16 max_mtu;

	u16 min_mtu;

	u32 rpm_dwrr_mtu;

	u32 sdp_dwrr_mtu;

	u64 rsvd[16]; /* Add reserved fields for future expansion */

};



struct nix_bandprof_alloc_req {

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

+15 −0
Original line number Diff line number Diff line
@@ -2802,6 +2802,7 @@ int rvu_mbox_handler_nix_get_hw_info(struct rvu *rvu, struct msg_req *req, 
				     struct nix_hw_info *rsp)

{

	u16 pcifunc = req->hdr.pcifunc;

	u64 dwrr_mtu;

	int blkaddr;



	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
@@ -2814,6 +2815,20 @@ int rvu_mbox_handler_nix_get_hw_info(struct rvu *rvu, struct msg_req *req, 
		rvu_get_lmac_link_max_frs(rvu, &rsp->max_mtu);



	rsp->min_mtu = NIC_HW_MIN_FRS;



	if (!rvu->hw->cap.nix_common_dwrr_mtu) {

		/* Return '1' on OTx2 */

		rsp->rpm_dwrr_mtu = 1;

		rsp->sdp_dwrr_mtu = 1;

		return 0;

	}



	dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_RPM_MTU);

	rsp->rpm_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu);



	dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_SDP_MTU);

	rsp->sdp_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu);



	return 0;

}

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c

+1 −2
Original line number Diff line number Diff line
@@ -92,8 +92,7 @@ int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 
	aq->sq.ena = 1;

	/* Only one SMQ is allocated, map all SQ's to that SMQ  */

	aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0];

	/* FIXME: set based on NIX_AF_DWRR_RPM_MTU*/

	aq->sq.smq_rr_weight = pfvf->netdev->mtu;

	aq->sq.smq_rr_weight = mtu_to_dwrr_weight(pfvf, pfvf->max_frs);

	aq->sq.default_chan = pfvf->hw.tx_chan_base;

	aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */

	aq->sq.sqb_aura = sqb_aura;

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h

+14 −0
Original line number Diff line number Diff line
@@ -9,6 +9,20 @@ 


#include "otx2_common.h"



static inline int mtu_to_dwrr_weight(struct otx2_nic *pfvf, int mtu)

{

	u32 weight;



	/* On OTx2, since AF returns DWRR_MTU as '1', this logic

	 * will work on those silicons as well.

	 */

	weight = mtu / pfvf->hw.dwrr_mtu;

	if (mtu % pfvf->hw.dwrr_mtu)

		weight += 1;



	return weight;

}



void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);

void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx);

int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);