Commit c3719bd9 authored by Pierre Gondois's avatar Pierre Gondois Committed by Sudeep Holla
Browse files

cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation 



RISC-V's implementation of init_of_cache_level() is following
the Devicetree Specification v0.3 regarding caches, cf.:
- s3.7.3 'Internal (L1) Cache Properties'
- s3.8 'Multi-level and Shared Cache Nodes'

Allow reusing the implementation by moving it.

Also make 'levels', 'leaves' and 'level' unsigned int.

Signed-off-by: default avatarPierre Gondois <pierre.gondois@arm.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230104183033.755668-2-pierre.gondois@arm.com


Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 1b929c02

arch/riscv/kernel/cacheinfo.c

+1 −38
Original line number Diff line number Diff line
@@ -115,44 +115,7 @@ static void fill_cacheinfo(struct cacheinfo **this_leaf, 


int init_cache_level(unsigned int cpu)

{

	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);

	struct device_node *np = of_cpu_device_node_get(cpu);

	struct device_node *prev = NULL;

	int levels = 0, leaves = 0, level;



	if (of_property_read_bool(np, "cache-size"))

		++leaves;

	if (of_property_read_bool(np, "i-cache-size"))

		++leaves;

	if (of_property_read_bool(np, "d-cache-size"))

		++leaves;

	if (leaves > 0)

		levels = 1;



	prev = np;

	while ((np = of_find_next_cache_node(np))) {

		of_node_put(prev);

		prev = np;

		if (!of_device_is_compatible(np, "cache"))

			break;

		if (of_property_read_u32(np, "cache-level", &level))

			break;

		if (level <= levels)

			break;

		if (of_property_read_bool(np, "cache-size"))

			++leaves;

		if (of_property_read_bool(np, "i-cache-size"))

			++leaves;

		if (of_property_read_bool(np, "d-cache-size"))

			++leaves;

		levels = level;

	}



	of_node_put(np);

	this_cpu_ci->num_levels = levels;

	this_cpu_ci->num_leaves = leaves;



	return 0;

	return init_of_cache_level(cpu);

}



int populate_cache_leaves(unsigned int cpu)

drivers/base/cacheinfo.c

+44 −0
Original line number Diff line number Diff line
@@ -229,8 +229,52 @@ static int cache_setup_of_node(unsigned int cpu) 


	return 0;

}



int init_of_cache_level(unsigned int cpu)

{

	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);

	struct device_node *np = of_cpu_device_node_get(cpu);

	struct device_node *prev = NULL;

	unsigned int levels = 0, leaves = 0, level;



	if (of_property_read_bool(np, "cache-size"))

		++leaves;

	if (of_property_read_bool(np, "i-cache-size"))

		++leaves;

	if (of_property_read_bool(np, "d-cache-size"))

		++leaves;

	if (leaves > 0)

		levels = 1;



	prev = np;

	while ((np = of_find_next_cache_node(np))) {

		of_node_put(prev);

		prev = np;

		if (!of_device_is_compatible(np, "cache"))

			break;

		if (of_property_read_u32(np, "cache-level", &level))

			break;

		if (level <= levels)

			break;

		if (of_property_read_bool(np, "cache-size"))

			++leaves;

		if (of_property_read_bool(np, "i-cache-size"))

			++leaves;

		if (of_property_read_bool(np, "d-cache-size"))

			++leaves;

		levels = level;

	}



	of_node_put(np);

	this_cpu_ci->num_levels = levels;

	this_cpu_ci->num_leaves = leaves;



	return 0;

}



#else

static inline int cache_setup_of_node(unsigned int cpu) { return 0; }

int init_of_cache_level(unsigned int cpu) { return 0; }

#endif



int __weak cache_setup_acpi(unsigned int cpu)

include/linux/cacheinfo.h

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ struct cpu_cacheinfo { 


struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);

int init_cache_level(unsigned int cpu);

int init_of_cache_level(unsigned int cpu);

int populate_cache_leaves(unsigned int cpu);

int cache_setup_acpi(unsigned int cpu);

bool last_level_cache_is_valid(unsigned int cpu);