Loading Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +1 −2 Original line number Diff line number Diff line Loading @@ -13,8 +13,7 @@ Required properties: Optional property: - big-endian: If present the dspi device's registers are implemented in big endian mode, otherwise in native mode(same with CPU), for more detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. in big endian mode. Optional SPI slave node properties: - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip Loading drivers/spi/Kconfig +0 −2 Original line number Diff line number Diff line Loading @@ -410,7 +410,6 @@ config SPI_OMAP_UWIRE config SPI_OMAP24XX tristate "McSPI driver for OMAP" depends on HAS_DMA depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH depends on ARCH_OMAP2PLUS || COMPILE_TEST help SPI master controller for OMAP24XX and later Multichannel SPI Loading Loading @@ -469,7 +468,6 @@ config SPI_PXA2XX_PCI config SPI_ROCKCHIP tristate "Rockchip SPI controller driver" depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH help This selects a driver for Rockchip SPI controller. Loading drivers/spi/spi-dw-pci.c +1 −1 Original line number Diff line number Diff line Loading @@ -67,7 +67,7 @@ static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) dws->irq = pdev->irq; /* * Specific handling for paltforms, like dma setup, * Specific handling for platforms, like dma setup, * clock rate, FIFO depth. */ if (desc) { Loading drivers/spi/spi-fsl-dspi.c +7 −0 Original line number Diff line number Diff line Loading @@ -121,18 +121,22 @@ enum dspi_trans_mode { struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; }; static const struct fsl_dspi_devtype_data vf610_data = { .trans_mode = DSPI_EOQ_MODE, .max_clock_factor = 2, }; static const struct fsl_dspi_devtype_data ls1021a_v1_data = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, }; static const struct fsl_dspi_devtype_data ls2085a_data = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, }; struct fsl_dspi { Loading Loading @@ -726,6 +730,9 @@ static int dspi_probe(struct platform_device *pdev) } clk_prepare_enable(dspi->clk); master->max_speed_hz = clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; init_waitqueue_head(&dspi->waitq); platform_set_drvdata(pdev, master); Loading drivers/spi/spi-fsl-espi.c +25 −5 Original line number Diff line number Diff line Loading @@ -245,7 +245,12 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) if (ret) return ret; wait_for_completion(&mpc8xxx_spi->done); /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ); if (ret == 0) dev_err(mpc8xxx_spi->dev, "Transaction hanging up (left %d bytes)\n", mpc8xxx_spi->count); /* disable rx ints */ mpc8xxx_spi_write_reg(®_base->mask, 0); Loading Loading @@ -539,16 +544,31 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) if (events & SPIE_NE) { u32 rx_data, tmp; u8 rx_data_8; int rx_nr_bytes = 4; int ret; /* Spin until RX is done */ while (SPIE_RXCNT(events) < min(4, mspi->len)) { cpu_relax(); events = mpc8xxx_spi_read_reg(®_base->event); if (SPIE_RXCNT(events) < min(4, mspi->len)) { ret = spin_event_timeout( !(SPIE_RXCNT(events = mpc8xxx_spi_read_reg(®_base->event)) < min(4, mspi->len)), 10000, 0); /* 10 msec */ if (!ret) dev_err(mspi->dev, "tired waiting for SPIE_RXCNT\n"); } if (mspi->len >= 4) { rx_data = mpc8xxx_spi_read_reg(®_base->receive); } else if (mspi->len <= 0) { dev_err(mspi->dev, "unexpected RX(SPIE_NE) interrupt occurred,\n" "(local rxlen %d bytes, reg rxlen %d bytes)\n", min(4, mspi->len), SPIE_RXCNT(events)); rx_nr_bytes = 0; } else { rx_nr_bytes = mspi->len; tmp = mspi->len; rx_data = 0; while (tmp--) { Loading @@ -559,7 +579,7 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) rx_data <<= (4 - mspi->len) * 8; } mspi->len -= 4; mspi->len -= rx_nr_bytes; if (mspi->rx) mspi->get_rx(rx_data, mspi); Loading Loading
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +1 −2 Original line number Diff line number Diff line Loading @@ -13,8 +13,7 @@ Required properties: Optional property: - big-endian: If present the dspi device's registers are implemented in big endian mode, otherwise in native mode(same with CPU), for more detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. in big endian mode. Optional SPI slave node properties: - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip Loading
drivers/spi/Kconfig +0 −2 Original line number Diff line number Diff line Loading @@ -410,7 +410,6 @@ config SPI_OMAP_UWIRE config SPI_OMAP24XX tristate "McSPI driver for OMAP" depends on HAS_DMA depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH depends on ARCH_OMAP2PLUS || COMPILE_TEST help SPI master controller for OMAP24XX and later Multichannel SPI Loading Loading @@ -469,7 +468,6 @@ config SPI_PXA2XX_PCI config SPI_ROCKCHIP tristate "Rockchip SPI controller driver" depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH help This selects a driver for Rockchip SPI controller. Loading
drivers/spi/spi-dw-pci.c +1 −1 Original line number Diff line number Diff line Loading @@ -67,7 +67,7 @@ static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) dws->irq = pdev->irq; /* * Specific handling for paltforms, like dma setup, * Specific handling for platforms, like dma setup, * clock rate, FIFO depth. */ if (desc) { Loading
drivers/spi/spi-fsl-dspi.c +7 −0 Original line number Diff line number Diff line Loading @@ -121,18 +121,22 @@ enum dspi_trans_mode { struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; }; static const struct fsl_dspi_devtype_data vf610_data = { .trans_mode = DSPI_EOQ_MODE, .max_clock_factor = 2, }; static const struct fsl_dspi_devtype_data ls1021a_v1_data = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, }; static const struct fsl_dspi_devtype_data ls2085a_data = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, }; struct fsl_dspi { Loading Loading @@ -726,6 +730,9 @@ static int dspi_probe(struct platform_device *pdev) } clk_prepare_enable(dspi->clk); master->max_speed_hz = clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; init_waitqueue_head(&dspi->waitq); platform_set_drvdata(pdev, master); Loading
drivers/spi/spi-fsl-espi.c +25 −5 Original line number Diff line number Diff line Loading @@ -245,7 +245,12 @@ static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) if (ret) return ret; wait_for_completion(&mpc8xxx_spi->done); /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ); if (ret == 0) dev_err(mpc8xxx_spi->dev, "Transaction hanging up (left %d bytes)\n", mpc8xxx_spi->count); /* disable rx ints */ mpc8xxx_spi_write_reg(®_base->mask, 0); Loading Loading @@ -539,16 +544,31 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) if (events & SPIE_NE) { u32 rx_data, tmp; u8 rx_data_8; int rx_nr_bytes = 4; int ret; /* Spin until RX is done */ while (SPIE_RXCNT(events) < min(4, mspi->len)) { cpu_relax(); events = mpc8xxx_spi_read_reg(®_base->event); if (SPIE_RXCNT(events) < min(4, mspi->len)) { ret = spin_event_timeout( !(SPIE_RXCNT(events = mpc8xxx_spi_read_reg(®_base->event)) < min(4, mspi->len)), 10000, 0); /* 10 msec */ if (!ret) dev_err(mspi->dev, "tired waiting for SPIE_RXCNT\n"); } if (mspi->len >= 4) { rx_data = mpc8xxx_spi_read_reg(®_base->receive); } else if (mspi->len <= 0) { dev_err(mspi->dev, "unexpected RX(SPIE_NE) interrupt occurred,\n" "(local rxlen %d bytes, reg rxlen %d bytes)\n", min(4, mspi->len), SPIE_RXCNT(events)); rx_nr_bytes = 0; } else { rx_nr_bytes = mspi->len; tmp = mspi->len; rx_data = 0; while (tmp--) { Loading @@ -559,7 +579,7 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) rx_data <<= (4 - mspi->len) * 8; } mspi->len -= 4; mspi->len -= rx_nr_bytes; if (mspi->rx) mspi->get_rx(rx_data, mspi); Loading