Commit c350717e authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/kvm/errata' into for-next/core 

KVM CPU errata rework
(Andrew Scull and Marc Zyngier)
* for-next/kvm/errata:
  KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h
  arm64: Unify WORKAROUND_SPECULATIVE_AT_{NVHE,VHE}
parents d2786527 fe677be9

arch/arm64/Kconfig

+18 −21
Original line number Diff line number Diff line
@@ -528,13 +528,13 @@ config ARM64_ERRATUM_1418040 


	  If unsure, say Y.



config ARM64_WORKAROUND_SPECULATIVE_AT_VHE

config ARM64_WORKAROUND_SPECULATIVE_AT

	bool



config ARM64_ERRATUM_1165522

	bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	select ARM64_WORKAROUND_SPECULATIVE_AT

	help

	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
@@ -544,10 +544,23 @@ config ARM64_ERRATUM_1165522 


	  If unsure, say Y.



config ARM64_ERRATUM_1319367

	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT

	help

	  This option adds work arounds for ARM Cortex-A57 erratum 1319537

	  and A72 erratum 1319367



	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by

	  speculating an AT instruction during a guest context switch.



	  If unsure, say Y.



config ARM64_ERRATUM_1530923

	bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	select ARM64_WORKAROUND_SPECULATIVE_AT

	help

	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
@@ -576,22 +589,6 @@ config ARM64_ERRATUM_1286807 
	  invalidated has been observed by other observers. The

	  workaround repeats the TLBI+DSB operation.



config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE

	bool



config ARM64_ERRATUM_1319367

	bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE

	help

	  This option adds work arounds for ARM Cortex-A57 erratum 1319537

	  and A72 erratum 1319367



	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by

	  speculating an AT instruction during a guest context switch.



	  If unsure, say Y.



config ARM64_ERRATUM_1463225

	bool "Cortex-A76: Software Step might prevent interrupt recognition"

	default y

arch/arm64/include/asm/cpucaps.h

+9 −10
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ 
#define ARM64_SSBS				34

#define ARM64_WORKAROUND_1418040		35

#define ARM64_HAS_SB				36

#define ARM64_WORKAROUND_SPECULATIVE_AT_VHE	37

#define ARM64_WORKAROUND_SPECULATIVE_AT		37

#define ARM64_HAS_ADDRESS_AUTH_ARCH		38

#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF		39

#define ARM64_HAS_GENERIC_AUTH_ARCH		40
@@ -55,15 +55,14 @@ 
#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM	45

#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM	46

#define ARM64_WORKAROUND_1542419		47

#define ARM64_WORKAROUND_SPECULATIVE_AT_NVHE	48

#define ARM64_HAS_E0PD				49

#define ARM64_HAS_RNG				50

#define ARM64_HAS_AMU_EXTN			51

#define ARM64_HAS_ADDRESS_AUTH			52

#define ARM64_HAS_GENERIC_AUTH			53

#define ARM64_HAS_32BIT_EL1			54

#define ARM64_BTI				55

#define ARM64_HAS_E0PD				48

#define ARM64_HAS_RNG				49

#define ARM64_HAS_AMU_EXTN			50

#define ARM64_HAS_ADDRESS_AUTH			51

#define ARM64_HAS_GENERIC_AUTH			52

#define ARM64_HAS_32BIT_EL1			53

#define ARM64_BTI				54



#define ARM64_NCAPS				56

#define ARM64_NCAPS				55



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/kvm_host.h

+0 −4
Original line number Diff line number Diff line
@@ -573,10 +573,6 @@ static inline bool kvm_arch_requires_vhe(void) 
	if (system_supports_sve())

		return true;



	/* Some implementations have defects that confine them to VHE */

	if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE))

		return true;



	return false;

}

arch/arm64/include/asm/kvm_hyp.h

+0 −18
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 
#include <linux/compiler.h>

#include <linux/kvm_host.h>

#include <asm/alternative.h>

#include <asm/kvm_mmu.h>

#include <asm/sysreg.h>



#define __hyp_text __section(.hyp.text) notrace
@@ -88,22 +87,5 @@ void deactivate_traps_vhe_put(void); 
u64 __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host_ctxt);

void __noreturn __hyp_do_panic(unsigned long, ...);



/*

 * Must be called from hyp code running at EL2 with an updated VTTBR

 * and interrupts disabled.

 */

static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm)

{

	write_sysreg(kvm->arch.vtcr, vtcr_el2);

	write_sysreg(kvm_get_vttbr(kvm), vttbr_el2);



	/*

	 * ARM errata 1165522 and 1530923 require the actual execution of the

	 * above before we can switch to the EL1/EL0 translation regime used by

	 * the guest.

	 */

	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));

}



#endif /* __ARM64_KVM_HYP_H__ */

arch/arm64/include/asm/kvm_mmu.h

+17 −0
Original line number Diff line number Diff line
@@ -604,5 +604,22 @@ static __always_inline u64 kvm_get_vttbr(struct kvm *kvm) 
	return kvm_phys_to_vttbr(baddr) | vmid_field | cnp;

}



/*

 * Must be called from hyp code running at EL2 with an updated VTTBR

 * and interrupts disabled.

 */

static __always_inline void __load_guest_stage2(struct kvm *kvm)

{

	write_sysreg(kvm->arch.vtcr, vtcr_el2);

	write_sysreg(kvm_get_vttbr(kvm), vttbr_el2);



	/*

	 * ARM errata 1165522 and 1530923 require the actual execution of the

	 * above before we can switch to the EL1/EL0 translation regime used by

	 * the guest.

	 */

	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));

}



#endif /* __ASSEMBLY__ */

#endif /* __ARM64_KVM_MMU_H__ */