Commit c346ff5c authored by Kieran Bingham's avatar Kieran Bingham Committed by Geert Uytterhoeven
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clk: renesas: r8a779a0: Add the DSI clocks 



The DSI clock is incorrectly defined as a fixed clock. This
demonstrates itself as the dsi-encoders failing to correctly enable and
start their PPI and HS clocks internally, and causes failures.

Move the DSI parent clock to match the updates in the BSP, which
resolves the initialisation procedures.

Signed-off-by: default avatarKieran Bingham <kieran.bingham@ideasonboard.com>
Fixes: 17bcc803 ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Link: https://lore.kernel.org/r/20210622232711.3219697-3-kieran.bingham@ideasonboard.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 417ed58d

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+3 −1
Original line number Diff line number Diff line
@@ -135,7 +135,6 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_FIXED("zt",		R8A779A0_CLK_ZT,	CLK_PLL1_DIV2,	2, 1),

	DEF_FIXED("ztr",	R8A779A0_CLK_ZTR,	CLK_PLL1_DIV2,	2, 1),

	DEF_FIXED("zr",		R8A779A0_CLK_ZR,	CLK_PLL1_DIV2,	1, 1),

	DEF_FIXED("dsi",	R8A779A0_CLK_DSI,	CLK_PLL5_DIV4,	1, 1),

	DEF_FIXED("cnndsp",	R8A779A0_CLK_CNNDSP,	CLK_PLL5_DIV4,	1, 1),

	DEF_FIXED("vip",	R8A779A0_CLK_VIP,	CLK_PLL5,	5, 1),

	DEF_FIXED("adgh",	R8A779A0_CLK_ADGH,	CLK_PLL5_DIV4,	1, 1),
@@ -151,6 +150,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),

	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),

	DEF_DIV6P1("csi0",	R8A779A0_CLK_CSI0,	CLK_PLL5_DIV4,	0x880),

	DEF_DIV6P1("dsi",	R8A779A0_CLK_DSI,	CLK_PLL5_DIV4,	0x884),



	DEF_OSC("osc",		R8A779A0_CLK_OSC,	CLK_EXTAL,	8),

	DEF_MDSEL("r",		R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
@@ -168,6 +168,8 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("csi42",	401,	R8A779A0_CLK_CSI0),

	DEF_MOD("csi43",	402,	R8A779A0_CLK_CSI0),

	DEF_MOD("du",		411,	R8A779A0_CLK_S3D1),

	DEF_MOD("dsi0",		415,	R8A779A0_CLK_DSI),

	DEF_MOD("dsi1",		416,	R8A779A0_CLK_DSI),

	DEF_MOD("fcpvd0",	508,	R8A779A0_CLK_S3D1),

	DEF_MOD("fcpvd1",	509,	R8A779A0_CLK_S3D1),

	DEF_MOD("hscif0",	514,	R8A779A0_CLK_S1D2),