Loading arch/arc/kernel/head.S +4 −3 Original line number Diff line number Diff line Loading @@ -24,13 +24,13 @@ .globl stext stext: ;------------------------------------------------------------------- ; Don't clobber r0-r4 yet. It might have bootloader provided info ; Don't clobber r0-r2 yet. It might have bootloader provided info ;------------------------------------------------------------------- sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] #ifdef CONFIG_SMP ; Only Boot (Master) proceeds. Others wait in platform dependent way ; Ensure Boot (Master) proceeds. Others wait in platform dependent way ; IDENTITY Reg [ 3 2 1 0 ] ; (cpu-id) ^^^ => Zero for UP ARC700 ; => #Core-ID if SMP (Master 0) Loading @@ -39,7 +39,8 @@ stext: ; need to make sure only boot cpu takes this path. GET_CPU_ID r5 cmp r5, 0 jnz arc_platform_smp_wait_to_boot mov.ne r0, r5 jne arc_platform_smp_wait_to_boot #endif ; Clear BSS before updating any globals ; XXX: use ZOL here Loading arch/arc/mm/cache_arc700.c +1 −2 Original line number Diff line number Diff line Loading @@ -100,10 +100,9 @@ #define DC_CTRL_INV_MODE_FLUSH 0x40 #define DC_CTRL_FLUSH_STATUS 0x100 char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len) char *arc_cache_mumbojumbo(int c, char *buf, int len) { int n = 0; unsigned int c = smp_processor_id(); #define PR_CACHE(p, enb, str) \ { \ Loading Loading
arch/arc/kernel/head.S +4 −3 Original line number Diff line number Diff line Loading @@ -24,13 +24,13 @@ .globl stext stext: ;------------------------------------------------------------------- ; Don't clobber r0-r4 yet. It might have bootloader provided info ; Don't clobber r0-r2 yet. It might have bootloader provided info ;------------------------------------------------------------------- sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] #ifdef CONFIG_SMP ; Only Boot (Master) proceeds. Others wait in platform dependent way ; Ensure Boot (Master) proceeds. Others wait in platform dependent way ; IDENTITY Reg [ 3 2 1 0 ] ; (cpu-id) ^^^ => Zero for UP ARC700 ; => #Core-ID if SMP (Master 0) Loading @@ -39,7 +39,8 @@ stext: ; need to make sure only boot cpu takes this path. GET_CPU_ID r5 cmp r5, 0 jnz arc_platform_smp_wait_to_boot mov.ne r0, r5 jne arc_platform_smp_wait_to_boot #endif ; Clear BSS before updating any globals ; XXX: use ZOL here Loading
arch/arc/mm/cache_arc700.c +1 −2 Original line number Diff line number Diff line Loading @@ -100,10 +100,9 @@ #define DC_CTRL_INV_MODE_FLUSH 0x40 #define DC_CTRL_FLUSH_STATUS 0x100 char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len) char *arc_cache_mumbojumbo(int c, char *buf, int len) { int n = 0; unsigned int c = smp_processor_id(); #define PR_CACHE(p, enb, str) \ { \ Loading