Commit c31d7349 authored by Alex Elder's avatar Alex Elder Committed by David S. Miller
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net: ipa: inter-EE interrupts aren't always available

The GSI inter-EE interrupts are not supported prior to IPA v3.5.
Don't attempt to initialize them in gsi_irq_setup() for hardware
that does not support them.

Originally proposed by AngeloGioacchino Del Regno.

Link: https://lore.kernel.org/netdev/20210211175015.200772-4-angelogioacchino.delregno@somainline.org


Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Acked-by: AngeloGioacchino Del Regno
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2afd6c8b
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+10 −3
Original line number Diff line number Diff line
@@ -210,9 +210,16 @@ static void gsi_irq_setup(struct gsi *gsi)
	iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);

	/* The inter-EE registers are in the non-adjusted address range */
	iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET);
	iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET);
	/* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */
	if (gsi->version > IPA_VERSION_3_1) {
		u32 offset;

		/* These registers are in the non-adjusted address range */
		offset = GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET;
		iowrite32(0, gsi->virt_raw + offset);
		offset = GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET;
		iowrite32(0, gsi->virt_raw + offset);
	}

	iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
}
+2 −1
Original line number Diff line number Diff line
@@ -52,7 +52,8 @@
 */
#define GSI_EE_REG_ADJUST			0x0000d000	/* IPA v4.5+ */

/* The two inter-EE IRQ register offsets are relative to gsi->virt_raw */
/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */

#define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \
			GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
#define GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(ee) \