Commit c309f7f4 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'for_3.10/omap_generic_cleanup_v2' of... 

Merge branch 'for_3.10/omap_generic_cleanup_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux into omap-for-v3.10/cleanup-v2
parents cdcbdfb2 fd1c0786

arch/arm/mach-omap2/cpuidle34xx.c

+0 −3
Original line number Diff line number Diff line
@@ -107,8 +107,6 @@ static int __omap3_enter_idle(struct cpuidle_device *dev, 
{

	struct omap3_idle_statedata *cx = &omap3_idle_data[index];



	local_fiq_disable();



	if (omap_irq_pending() || need_resched())

		goto return_sleep_time;
@@ -143,7 +141,6 @@ static int __omap3_enter_idle(struct cpuidle_device *dev, 
		clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);



return_sleep_time:

	local_fiq_enable();



	return index;

}

arch/arm/mach-omap2/cpuidle44xx.c

+0 −7
Original line number Diff line number Diff line
@@ -70,10 +70,7 @@ static int omap4_enter_idle_simple(struct cpuidle_device *dev, 
			struct cpuidle_driver *drv,

			int index)

{

	local_fiq_disable();

	omap_do_wfi();

	local_fiq_enable();



	return index;

}
@@ -84,8 +81,6 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev, 
	struct omap4_idle_statedata *cx = &omap4_idle_data[index];

	int cpu_id = smp_processor_id();



	local_fiq_disable();



	/*

	 * CPU0 has to wait and stay ON until CPU1 is OFF state.

	 * This is necessary to honour hardware recommondation
@@ -158,8 +153,6 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev, 
	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);

	cpu_done[dev->cpu] = false;



	local_fiq_enable();



	return index;

}

arch/arm/mach-omap2/omap-hotplug.c

+0 −6
Original line number Diff line number Diff line
@@ -19,11 +19,8 @@ 
#include <linux/smp.h>

#include <linux/io.h>



#include <asm/cacheflush.h>

#include "omap-wakeupgen.h"



#include "common.h"



#include "powerdomain.h"



/*
@@ -35,9 +32,6 @@ void __ref omap4_cpu_die(unsigned int cpu) 
	unsigned int boot_cpu = 0;

	void __iomem *base = omap_get_wakeupgen_base();



	flush_cache_all();

	dsb();



	/*

	 * we're ready for shutdown now, so do it

	 */

arch/arm/mach-omap2/omap-smp.c

+20 −37
Original line number Diff line number Diff line
@@ -21,7 +21,6 @@ 
#include <linux/io.h>

#include <linux/irqchip/arm-gic.h>



#include <asm/cacheflush.h>

#include <asm/smp_scu.h>



#include "omap-secure.h"
@@ -103,9 +102,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * 
	else

		__raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);



	flush_cache_all();

	smp_wmb();



	if (!cpu1_clkdm)

		cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
@@ -168,38 +164,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * 
	return 0;

}



static void __init wakeup_secondary(void)

{

	void *startup_addr = omap_secondary_startup;

	void __iomem *base = omap_get_wakeupgen_base();



	if (cpu_is_omap446x()) {

		startup_addr = omap_secondary_startup_4460;

		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;

	}



	/*

	 * Write the address of secondary startup routine into the

	 * AuxCoreBoot1 where ROM code will jump and start executing

	 * on secondary core once out of WFE

	 * A barrier is added to ensure that write buffer is drained

	 */

	if (omap_secure_apis_support())

		omap_auxcoreboot_addr(virt_to_phys(startup_addr));

	else

		__raw_writel(virt_to_phys(omap5_secondary_startup),

						base + OMAP_AUX_CORE_BOOT_1);



	smp_wmb();



	/*

	 * Send a 'sev' to wake the secondary core from WFE.

	 * Drain the outstanding writes to memory

	 */

	dsb_sev();

	mb();

}



/*

 * Initialise the CPU possible map early - this describes the CPUs

 * which may be present or become present in the system.
@@ -235,6 +199,8 @@ static void __init omap4_smp_init_cpus(void) 


static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)

{

	void *startup_addr = omap_secondary_startup;

	void __iomem *base = omap_get_wakeupgen_base();



	/*

	 * Initialise the SCU and wake up the secondary core using
@@ -242,7 +208,24 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) 
	 */

	if (scu_base)

		scu_enable(scu_base);

	wakeup_secondary();



	if (cpu_is_omap446x()) {

		startup_addr = omap_secondary_startup_4460;

		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;

	}



	/*

	 * Write the address of secondary startup routine into the

	 * AuxCoreBoot1 where ROM code will jump and start executing

	 * on secondary core once out of WFE

	 * A barrier is added to ensure that write buffer is drained

	 */

	if (omap_secure_apis_support())

		omap_auxcoreboot_addr(virt_to_phys(startup_addr));

	else

		__raw_writel(virt_to_phys(omap5_secondary_startup),

						base + OMAP_AUX_CORE_BOOT_1);



}



struct smp_operations omap4_smp_ops __initdata = {

arch/arm/mach-omap2/omap4-common.c

+16 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include <linux/of_platform.h>

#include <linux/export.h>

#include <linux/irqchip/arm-gic.h>

#include <linux/of_address.h>



#include <asm/hardware/cache-l2x0.h>

#include <asm/mach/map.h>
@@ -258,6 +259,21 @@ omap_early_initcall(omap4_sar_ram_init); 


void __init omap_gic_of_init(void)

{

	struct device_node *np;



	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */

	if (!cpu_is_omap446x())

		goto skip_errata_init;



	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");

	gic_dist_base_addr = of_iomap(np, 0);

	WARN_ON(!gic_dist_base_addr);



	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");

	twd_base = of_iomap(np, 0);

	WARN_ON(!twd_base);



skip_errata_init:

	omap_wakeupgen_init();

	irqchip_init();

}