Commit c305ae99 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2021-11-30' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



drm/i915 feature pull for v5.17:

Features and functionality:
- Implement per-lane DP drive settings for ICL+ (Ville)
- Enable runtime pm autosuspend by default (Tilak Tangudu)
- ADL-P DSI support (Vandita)
- Add support for pipe C and D DMC firmware (Anusha)
- Implement (near)atomic gamma LUT updates via vblank workers (Ville)
- Split plane updates to noarm+arm phases (Ville)
- Remove the CCS FB stride restrictions on ADL-P (Imre)
- Add PSR selective fetch support for biplanar formats (Jouni)
- Add support for display audio codec keepalive (Kai)
- VRR platform support for display 11 (Manasi)

Refactoring and cleanups:
- FBC refactoring and cleanups preparing for multiple FBC instances (Ville)
- PCH modeset refactoring, move to its own file (Ville)
- Refactor and simplify handling of modifiers (Imre)
- PXP cleanups (Ville)
- Display header and include refactoring (Jani)
- Some register macro cleanups (Ville)
- Refactor DP HDMI DFP limit code (Ville)

Fixes:
- Disable DSB usage for now due to incorrect gamma LUT updates (Ville)
- Check async flip state of every crtc and plane only once (José)
- Fix DPT FB suspend/resume (Imre)
- Fix black screen on reboot due to disabled DP++ TMDS output buffers (Ville)
- Don't request GMBUS to generate irqs when called while irqs are off (Ville)
- Fix type1 DVI DP dual mode adapter heuristics for modern platforms (Ville)
- Fix fix integer overflow in 128b/132b data rate calculation (Jani)
- Fix bigjoiner state readout (Ville)
- Build fix for non-x86 (Siva)
- PSR fixes (José, Jouni, Ville)
- Disable ADL-P underrun recovery (José)
- Fix DP link parameter usage before valid DPCD (Imre)
- VRR vblank and frame counter fixes (Ville)
- Fix fastsets on TypeC ports following a non-blocking modeset (Imre)
- Compiler warning fixes (Nathan Chancellor)
- Fix DSI HS mode commands (William Tseng)
- Error return fixes (Dan Carpenter)
- Update memory bandwidth calculations (Radhakrishna)
- Implement WM0 cursor WA for DG2 (Stan)
- Fix DSI Double pixelclock on read-back for dual-link panels (Hans de Goede)
- HDMI 2.1 PCON FRL configuration fixes (Ankit)

Merges:
- DP link training delay helpers, via topic branch (Jani)
- Backmerge drm-next (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87v909it0t.fsf@intel.com
parents c18c8891 74ba89c0

drivers/char/agp/intel-gtt.c

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include <linux/kernel.h>

#include <linux/pagemap.h>

#include <linux/agp_backend.h>

#include <linux/intel-iommu.h>

#include <linux/delay.h>

#include <asm/smp.h>

#include "agp.h"

drivers/gpu/drm/i915/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ config DRM_I915 
	select ACPI_VIDEO if ACPI

	select ACPI_BUTTON if ACPI

	select SYNC_FILE

	select IOSF_MBI

	select IOSF_MBI if X86

	select CRC32

	select SND_HDA_I915 if SND_HDA_CORE

	select CEC_CORE if CEC_NOTIFIER

drivers/gpu/drm/i915/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ subdir-ccflags-y += -I$(srctree)/$(src) 
# Please keep these build lists sorted!



# core driver code

i915-y += i915_drv.o \

i915-y += i915_driver.o \

	  i915_config.o \

	  i915_irq.o \

	  i915_getparam.o \
@@ -226,6 +226,8 @@ i915-y += \ 
	display/intel_hotplug.o \

	display/intel_lpe_audio.o \

	display/intel_overlay.o \

	display/intel_pch_display.o \

	display/intel_pch_refclk.o \

	display/intel_plane_initial.o \

	display/intel_psr.o \

	display/intel_quirks.o \

drivers/gpu/drm/i915/display/i9xx_plane.c

+80 −54
Original line number Diff line number Diff line
@@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = { 
	DRM_FORMAT_XBGR16161616F,

};



static const u64 i9xx_format_modifiers[] = {

	I915_FORMAT_MOD_X_TILED,

	DRM_FORMAT_MOD_LINEAR,

	DRM_FORMAT_MOD_INVALID

};



static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,

					    u32 format, u64 modifier)

{

	switch (modifier) {

	case DRM_FORMAT_MOD_LINEAR:

	case I915_FORMAT_MOD_X_TILED:

		break;

	default:

	if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))

		return false;

	}



	switch (format) {

	case DRM_FORMAT_C8:
@@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, 
static bool i965_plane_format_mod_supported(struct drm_plane *_plane,

					    u32 format, u64 modifier)

{

	switch (modifier) {

	case DRM_FORMAT_MOD_LINEAR:

	case I915_FORMAT_MOD_X_TILED:

		break;

	default:

	if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))

		return false;

	}



	switch (format) {

	case DRM_FORMAT_C8:
@@ -272,7 +256,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 
		u32 alignment = intel_surf_alignment(fb, 0);

		int cpp = fb->format->cpp[0];



		while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].stride) {

		while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) {

			if (offset == 0) {

				drm_dbg_kms(&dev_priv->drm,

					    "Unable to find suitable display surface offset due to X-tiling\n");
@@ -418,22 +402,49 @@ static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 
	return DIV_ROUND_UP(pixel_rate * num, den);

}



static void i9xx_update_plane(struct intel_plane *plane,

static void i9xx_plane_update_noarm(struct intel_plane *plane,

				    const struct intel_crtc_state *crtc_state,

				    const struct intel_plane_state *plane_state)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	u32 linear_offset;

	int x = plane_state->view.color_plane[0].x;

	int y = plane_state->view.color_plane[0].y;

	unsigned long irqflags;



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),

			  plane_state->view.color_plane[0].mapping_stride);



	if (DISPLAY_VER(dev_priv) < 4) {

		int crtc_x = plane_state->uapi.dst.x1;

		int crtc_y = plane_state->uapi.dst.y1;

		int crtc_w = drm_rect_width(&plane_state->uapi.dst);

		int crtc_h = drm_rect_height(&plane_state->uapi.dst);



		/*

		 * PLANE_A doesn't actually have a full window

		 * generator but let's assume we still need to

		 * program whatever is there.

		 */

		intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),

				  (crtc_y << 16) | crtc_x);

		intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),

				  ((crtc_h - 1) << 16) | (crtc_w - 1));

	}



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static void i9xx_plane_update_arm(struct intel_plane *plane,

				  const struct intel_crtc_state *crtc_state,

				  const struct intel_plane_state *plane_state)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	int x = plane_state->view.color_plane[0].x;

	int y = plane_state->view.color_plane[0].y;

	u32 dspcntr, dspaddr_offset, linear_offset;

	unsigned long irqflags;

	u32 dspaddr_offset;

	u32 dspcntr;



	dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
@@ -446,20 +457,12 @@ static void i9xx_update_plane(struct intel_plane *plane, 


	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),

			  plane_state->view.color_plane[0].stride);

	if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {

		int crtc_x = plane_state->uapi.dst.x1;

		int crtc_y = plane_state->uapi.dst.y1;

		int crtc_w = drm_rect_width(&plane_state->uapi.dst);

		int crtc_h = drm_rect_height(&plane_state->uapi.dst);



	if (DISPLAY_VER(dev_priv) < 4) {

		/*

		 * PLANE_A doesn't actually have a full window

		 * generator but let's assume we still need to

		 * program whatever is there.

		 */

		intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),

				  (crtc_y << 16) | crtc_x);

		intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),

				  ((crtc_h - 1) << 16) | (crtc_w - 1));

	} else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {

		intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),

				  (crtc_y << 16) | crtc_x);

		intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
@@ -493,7 +496,21 @@ static void i9xx_update_plane(struct intel_plane *plane, 
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static void i9xx_disable_plane(struct intel_plane *plane,

static void i830_plane_update_arm(struct intel_plane *plane,

				  const struct intel_crtc_state *crtc_state,

				  const struct intel_plane_state *plane_state)

{

	/*

	 * On i830/i845 all registers are self-arming [ALM040].

	 *

	 * Additional breakage on i830 causes register reads to return

	 * the last latched value instead of the last written value [ALM026].

	 */

	i9xx_plane_update_noarm(plane, crtc_state, plane_state);

	i9xx_plane_update_arm(plane, crtc_state, plane_state);

}



static void i9xx_plane_disable_arm(struct intel_plane *plane,

				   const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -768,6 +785,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
	struct intel_plane *plane;

	const struct drm_plane_funcs *plane_funcs;

	unsigned int supported_rotations;

	const u64 *modifiers;

	const u32 *formats;

	int num_formats;

	int ret, zpos;
@@ -789,12 +807,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
	plane->id = PLANE_PRIMARY;

	plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);



	plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);

	if (plane->has_fbc) {

		struct intel_fbc *fbc = &dev_priv->fbc;



		fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;

	}

	if (i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane))

		plane->fbc = &dev_priv->fbc;

	if (plane->fbc)

		plane->fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		formats = vlv_primary_formats;
@@ -851,8 +867,13 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
			plane->max_stride = ilk_primary_max_stride;

	}



	plane->update_plane = i9xx_update_plane;

	plane->disable_plane = i9xx_disable_plane;

	if (IS_I830(dev_priv) || IS_I845G(dev_priv)) {

		plane->update_arm = i830_plane_update_arm;

	} else {

		plane->update_noarm = i9xx_plane_update_noarm;

		plane->update_arm = i9xx_plane_update_arm;

	}

	plane->disable_arm = i9xx_plane_disable_arm;

	plane->get_hw_state = i9xx_plane_get_hw_state;

	plane->check_plane = i9xx_plane_check;
@@ -875,21 +896,26 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
		plane->disable_flip_done = ilk_primary_disable_flip_done;

	}



	modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X);



	if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))

		ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,

					       0, plane_funcs,

					       formats, num_formats,

					       i9xx_format_modifiers,

					       modifiers,

					       DRM_PLANE_TYPE_PRIMARY,

					       "primary %c", pipe_name(pipe));

	else

		ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,

					       0, plane_funcs,

					       formats, num_formats,

					       i9xx_format_modifiers,

					       modifiers,

					       DRM_PLANE_TYPE_PRIMARY,

					       "plane %c",

					       plane_name(plane->i9xx_plane));



	kfree(modifiers);



	if (ret)

		goto fail;

drivers/gpu/drm/i915/display/icl_dsi.c

+8 −2
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include <drm/drm_atomic_helper.h>

#include <drm/drm_mipi_dsi.h>



#include "icl_dsi.h"

#include "intel_atomic.h"

#include "intel_backlight.h"

#include "intel_combo_phy.h"
@@ -36,6 +37,7 @@ 
#include "intel_ddi.h"

#include "intel_de.h"

#include "intel_dsi.h"

#include "intel_dsi_vbt.h"

#include "intel_panel.h"

#include "intel_vdsc.h"

#include "skl_scaler.h"
@@ -183,6 +185,8 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 


	if (enable_lpdt)

		tmp |= LP_DATA_TRANSFER;

	else

		tmp &= ~LP_DATA_TRANSFER;



	tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);

	tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
@@ -1226,7 +1230,9 @@ static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 
	/* step5: program and powerup panel */

	gen11_dsi_powerup_panel(encoder);



	intel_dsc_enable(encoder, pipe_config);

	intel_dsc_dsi_pps_write(encoder, pipe_config);



	intel_dsc_enable(pipe_config);



	/* step6c: configure transcoder timings */

	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
@@ -1623,7 +1629,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 
	/* FIXME: initialize from VBT */

	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;



	ret = intel_dsc_compute_params(encoder, crtc_state);

	ret = intel_dsc_compute_params(crtc_state);

	if (ret)

		return ret;