Commit c2fe9ec3 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 

Tony Nguyen says:

====================
1GbE Intel Wired LAN Driver Updates 2022-07-18

This series contains updates to igc driver only.

Kurt Kanzenbach adds support for Qbv schedules where one queue stays open
in consecutive entries.

Sasha removes an unused define and field.

* '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
  igc: Remove forced_speed_duplex value
  igc: Remove MSI-X PBA Clear register
  igc: Lift TAPRIO schedule restriction
====================

Link: https://lore.kernel.org/r/20220718180109.4114540-1-anthony.l.nguyen@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents ca0cab11 6ac0db3f

drivers/net/ethernet/intel/igc/igc_hw.h

+0 −2
Original line number Diff line number Diff line
@@ -89,8 +89,6 @@ struct igc_mac_info { 
	u32 mta_shadow[MAX_MTA_REG];

	u16 rar_entry_count;



	u8 forced_speed_duplex;



	bool asf_firmware_present;

	bool arc_subsystem_valid;

drivers/net/ethernet/intel/igc/igc_main.c

+17 −6
Original line number Diff line number Diff line
@@ -5813,9 +5813,10 @@ static bool validate_schedule(struct igc_adapter *adapter, 
		return false;



	for (n = 0; n < qopt->num_entries; n++) {

		const struct tc_taprio_sched_entry *e;

		const struct tc_taprio_sched_entry *e, *prev;

		int i;



		prev = n ? &qopt->entries[n - 1] : NULL;

		e = &qopt->entries[n];



		/* i225 only supports "global" frame preemption
@@ -5828,7 +5829,12 @@ static bool validate_schedule(struct igc_adapter *adapter, 
			if (e->gate_mask & BIT(i))

				queue_uses[i]++;



			if (queue_uses[i] > 1)

			/* There are limitations: A single queue cannot be

			 * opened and closed multiple times per cycle unless the

			 * gate stays open. Check for it.

			 */

			if (queue_uses[i] > 1 &&

			    !(prev->gate_mask & BIT(i)))

				return false;

		}

	}
@@ -5872,6 +5878,7 @@ static int igc_tsn_clear_schedule(struct igc_adapter *adapter) 
static int igc_save_qbv_schedule(struct igc_adapter *adapter,

				 struct tc_taprio_qopt_offload *qopt)

{

	bool queue_configured[IGC_MAX_TX_QUEUES] = { };

	u32 start_time = 0, end_time = 0;

	size_t n;
@@ -5887,9 +5894,6 @@ static int igc_save_qbv_schedule(struct igc_adapter *adapter, 
	adapter->cycle_time = qopt->cycle_time;

	adapter->base_time = qopt->base_time;



	/* FIXME: be a little smarter about cases when the gate for a

	 * queue stays open for more than one entry.

	 */

	for (n = 0; n < qopt->num_entries; n++) {

		struct tc_taprio_sched_entry *e = &qopt->entries[n];

		int i;
@@ -5902,8 +5906,15 @@ static int igc_save_qbv_schedule(struct igc_adapter *adapter, 
			if (!(e->gate_mask & BIT(i)))

				continue;



			/* Check whether a queue stays open for more than one

			 * entry. If so, keep the start and advance the end

			 * time.

			 */

			if (!queue_configured[i])

				ring->start_time = start_time;

			ring->end_time = end_time;



			queue_configured[i] = true;

		}



		start_time += e->interval;

drivers/net/ethernet/intel/igc/igc_regs.h

+0 −3
Original line number Diff line number Diff line
@@ -59,9 +59,6 @@ 
#define IGC_IVAR_MISC		0x01740  /* IVAR for "other" causes - RW */

#define IGC_GPIE		0x01514  /* General Purpose Intr Enable - RW */



/* MSI-X Table Register Descriptions */

#define IGC_PBACL		0x05B68  /* MSIx PBA Clear - R/W 1 to clear */



/* RSS registers */

#define IGC_MRQC		0x05818 /* Multiple Receive Control - RW */