Commit c2c70752 authored by Matt Roper's avatar Matt Roper Committed by Radhakrishna Sripada
Browse files

drm/i915: Read graphics/media/display arch version from hw 



Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be read
directly from a register in the MMIO space.

Bspec: 63361, 64111

v2:
  - Move the IP version readout to intel_device_info.c
  - Convert the macro into a function

v3:
  - Move subplatform init to runtime early init
  - Cache runtime ver, release info to compare with hardware values.
  - Use IP_VER for snaity check(MattR)

v4:
  - Minor doccumentation changes.
  - Normalize HAS_GMD_ID macro value.(JaniN)

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220916014648.1310346-2-radhakrishna.sripada@intel.com
parent 958349ff

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+3 −0
Original line number Diff line number Diff line
@@ -39,6 +39,9 @@ 
#define FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0xd84)

#define FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0xd88)



#define GMD_ID_GRAPHICS				_MMIO(0xd8c)

#define GMD_ID_MEDIA				_MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)



#define MCFG_MCR_SELECTOR			_MMIO(0xfd0)

#define SF_MCR_SELECTOR				_MMIO(0xfd8)

#define GEN8_MCR_SELECTOR			_MMIO(0xfdc)

drivers/gpu/drm/i915/i915_driver.c

+2 −1
Original line number Diff line number Diff line
@@ -324,7 +324,8 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 
	if (i915_inject_probe_failure(dev_priv))

		return -ENODEV;



	intel_device_info_subplatform_init(dev_priv);

	intel_device_info_runtime_init_early(dev_priv);



	intel_step_init(dev_priv);



	intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -930,6 +930,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 


#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)



#define HAS_GMD_ID(i915)	(INTEL_INFO(i915)->has_gmd_id)



#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))



#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)

drivers/gpu/drm/i915/i915_pci.c

+1 −0
Original line number Diff line number Diff line
@@ -1128,6 +1128,7 @@ static const struct intel_device_info mtl_info = { 
	PLATFORM(INTEL_METEORLAKE),

	.display.has_modular_fia = 1,

	.has_flat_ccs = 0,

	.has_gmd_id = 1,

	.has_snoop = 1,

	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,

	.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),

drivers/gpu/drm/i915/i915_reg.h

+7 −0
Original line number Diff line number Diff line
@@ -5839,6 +5839,11 @@ 
#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)

#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)



#define GMD_ID_DISPLAY				_MMIO(0x510a0)

#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)

#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)

#define   GMD_ID_STEP				REG_GENMASK(5, 0)



/*GEN11 chicken */

#define _PIPEA_CHICKEN				0x70038

#define _PIPEB_CHICKEN				0x71038
@@ -8356,4 +8361,6 @@ enum skl_power_gate { 
#define   MTL_TRAS_MASK			REG_GENMASK(16, 8)

#define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)



#define MTL_MEDIA_GSI_BASE		0x380000



#endif /* _I915_REG_H_ */