Commit c2afeb79 authored by Sam Protsenko's avatar Sam Protsenko Committed by Sylwester Nawrocki
Browse files

dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP 



CMU_CMGP generates USI and ADC clocks for BLK_ALIVE. In particular USI
clocks are needed for HSI2C_3 and HSI2C_4 instances.

Add clock indices and bindings documentation for CMU_CMGP domain.

Signed-off-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211121232741.6967-4-semen.protsenko@linaro.org
parent 579839a9

Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml

+19 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ properties: 
    enum:

      - samsung,exynos850-cmu-top

      - samsung,exynos850-cmu-apm

      - samsung,exynos850-cmu-cmgp

      - samsung,exynos850-cmu-core

      - samsung,exynos850-cmu-dpu

      - samsung,exynos850-cmu-hsi
@@ -87,6 +88,24 @@ allOf: 
            - const: oscclk

            - const: dout_clkcmu_apm_bus



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos850-cmu-cmgp



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_CMGP bus clock (from CMU_APM)



        clock-names:

          items:

            - const: oscclk

            - const: gout_clkcmu_cmgp_bus



  - if:

      properties:

        compatible:

include/dt-bindings/clock/exynos850.h

+17 −0
Original line number Diff line number Diff line
@@ -84,6 +84,23 @@ 
#define CLK_GOUT_SPEEDY_PCLK		21

#define APM_NR_CLK			22



/* CMU_CMGP */

#define CLK_RCO_CMGP			1

#define CLK_MOUT_CMGP_ADC		2

#define CLK_MOUT_CMGP_USI0		3

#define CLK_MOUT_CMGP_USI1		4

#define CLK_DOUT_CMGP_ADC		5

#define CLK_DOUT_CMGP_USI0		6

#define CLK_DOUT_CMGP_USI1		7

#define CLK_GOUT_CMGP_ADC_S0_PCLK	8

#define CLK_GOUT_CMGP_ADC_S1_PCLK	9

#define CLK_GOUT_CMGP_GPIO_PCLK		10

#define CLK_GOUT_CMGP_USI0_IPCLK	11

#define CLK_GOUT_CMGP_USI0_PCLK		12

#define CLK_GOUT_CMGP_USI1_IPCLK	13

#define CLK_GOUT_CMGP_USI1_PCLK		14

#define CMGP_NR_CLK			15



/* CMU_HSI */

#define CLK_MOUT_HSI_BUS_USER		1

#define CLK_MOUT_HSI_MMC_CARD_USER	2