Commit c2aa552f authored by Matthew Brost's avatar Matthew Brost Committed by John Harrison
Browse files

drm/i915/guc: Add multi-lrc context registration 



Add multi-lrc context registration H2G. In addition a workqueue and
process descriptor are setup during multi-lrc context registration as
these data structures are needed for multi-lrc submission.

v2:
 (John Harrison)
  - Move GuC specific fields into sub-struct
  - Clean up WQ defines
  - Add comment explaining math to derive WQ / PD address
v3:
 (John Harrison)
  - Add PARENT_SCRATCH_SIZE define
  - Update comment explaining multi-lrc register
v4:
 (John Harrison)
  - Move PARENT_SCRATCH_SIZE to common file

Signed-off-by: default avatarMatthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211014172005.27155-9-matthew.brost@intel.com
parent 3897df4c

drivers/gpu/drm/i915/gt/intel_context.h

+2 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ void intel_context_free(struct intel_context *ce); 
int intel_context_reconfigure_sseu(struct intel_context *ce,

				   const struct intel_sseu sseu);



#define PARENT_SCRATCH_SIZE	PAGE_SIZE



static inline bool intel_context_is_child(struct intel_context *ce)

{

	return !!ce->parallel.parent;

drivers/gpu/drm/i915/gt/intel_context_types.h

+12 −0
Original line number Diff line number Diff line
@@ -239,6 +239,18 @@ struct intel_context { 
		struct intel_context *parent;

		/** @number_children: number of children if parent */

		u8 number_children;

		/** @guc: GuC specific members for parallel submission */

		struct {

			/** @wqi_head: head pointer in work queue */

			u16 wqi_head;

			/** @wqi_tail: tail pointer in work queue */

			u16 wqi_tail;

			/**

			 * @parent_page: page in context state (ce->state) used

			 * by parent for work queue, process descriptor

			 */

			u8 parent_page;

		} guc;

	} parallel;



#ifdef CONFIG_DRM_I915_SELFTEST

drivers/gpu/drm/i915/gt/intel_lrc.c

+5 −0
Original line number Diff line number Diff line
@@ -942,6 +942,11 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine) 
		context_size += PAGE_SIZE;

	}



	if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) {

		ce->parallel.guc.parent_page = context_size / PAGE_SIZE;

		context_size += PARENT_SCRATCH_SIZE;

	}



	obj = i915_gem_object_create_lmem(engine->i915, context_size,

					  I915_BO_ALLOC_PM_VOLATILE);

	if (IS_ERR(obj))

drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h

+1 −0
Original line number Diff line number Diff line
@@ -142,6 +142,7 @@ enum intel_guc_action { 
	INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,

	INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,

	INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,

	INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,

	INTEL_GUC_ACTION_RESET_CLIENT = 0x5507,

	INTEL_GUC_ACTION_LIMIT

};

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

+0 −2
Original line number Diff line number Diff line
@@ -52,8 +52,6 @@ 


#define GUC_DOORBELL_INVALID		256



#define GUC_WQ_SIZE			(PAGE_SIZE * 2)



/* Work queue item header definitions */

#define WQ_STATUS_ACTIVE		1

#define WQ_STATUS_SUSPENDED		2