Commit c276aae8 authored by Roi Dayan's avatar Roi Dayan Committed by Saeed Mahameed
Browse files

net/mlx5: Move mlx5e hw resources into a sub object 



This is to separate between resources attributes and other
attributes we will want to use.

Signed-off-by: default avatarRoi Dayan <roid@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent 5a65d85d

drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c

+2 −2
Original line number Diff line number Diff line
@@ -174,7 +174,7 @@ static int mlx5e_ptp_alloc_txqsq(struct mlx5e_port_ptp *c, int txq_ix, 
	sq->mdev      = mdev;

	sq->ch_ix     = c->ix;

	sq->txq_ix    = txq_ix;

	sq->uar_map   = mdev->mlx5e_res.bfreg.map;

	sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;

	sq->min_inline_mode = params->tx_min_inline_mode;

	sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);

	sq->stats     = &c->priv->port_ptp_stats.sq[tc];
@@ -475,7 +475,7 @@ int mlx5e_port_ptp_open(struct mlx5e_priv *priv, struct mlx5e_params *params, 
	c->ix       = 0;

	c->pdev     = mlx5_core_dma_dev(priv->mdev);

	c->netdev   = priv->netdev;

	c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);

	c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);

	c->num_tc   = params->num_tc;

	c->stats    = &priv->port_ptp_stats.ch;

	c->lag_port = lag_port;

drivers/net/ethernet/mellanox/mlx5/core/en/trap.c

+3 −3
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ static int mlx5e_alloc_trap_rq(struct mlx5e_priv *priv, struct mlx5e_rq_param *r 
	if (err)

		goto err_free_frags;



	rq->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);

	rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key);



	mlx5e_rq_set_trap_handlers(rq, params);
@@ -213,7 +213,7 @@ static int mlx5e_create_trap_direct_rq_tir(struct mlx5_core_dev *mdev, struct ml 
		return -ENOMEM;



	tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);

	MLX5_SET(tirc, tirc, transport_domain, mdev->mlx5e_res.td.tdn);

	MLX5_SET(tirc, tirc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);

	MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_NONE);

	MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);

	MLX5_SET(tirc, tirc, inline_rqn, rqn);
@@ -266,7 +266,7 @@ static struct mlx5e_trap *mlx5e_open_trap(struct mlx5e_priv *priv) 
	t->tstamp   = &priv->tstamp;

	t->pdev     = mlx5_core_dma_dev(priv->mdev);

	t->netdev   = priv->netdev;

	t->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);

	t->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);

	t->stats    = &priv->trap_stats.ch;



	netif_napi_add(netdev, &t->napi, mlx5e_trap_napi_poll, 64);

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ static int mlx5e_ktls_create_tir(struct mlx5_core_dev *mdev, u32 *tirn, u32 rqtn 


	tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);



	MLX5_SET(tirc, tirc, transport_domain, mdev->mlx5e_res.td.tdn);

	MLX5_SET(tirc, tirc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);

	MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);

	MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);

	MLX5_SET(tirc, tirc, indirect_table, rqtn);

drivers/net/ethernet/mellanox/mlx5/core/en_common.c

+15 −12
Original line number Diff line number Diff line
@@ -38,15 +38,16 @@ 


int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir, u32 *in)

{

	struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;

	int err;



	err = mlx5_core_create_tir(mdev, in, &tir->tirn);

	if (err)

		return err;



	mutex_lock(&mdev->mlx5e_res.td.list_lock);

	list_add(&tir->list, &mdev->mlx5e_res.td.tirs_list);

	mutex_unlock(&mdev->mlx5e_res.td.list_lock);

	mutex_lock(&res->td.list_lock);

	list_add(&tir->list, &res->td.tirs_list);

	mutex_unlock(&res->td.list_lock);



	return 0;

}
@@ -54,10 +55,12 @@ int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir, u32 *in) 
void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,

		       struct mlx5e_tir *tir)

{

	mutex_lock(&mdev->mlx5e_res.td.list_lock);

	struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;



	mutex_lock(&res->td.list_lock);

	mlx5_core_destroy_tir(mdev, tir->tirn);

	list_del(&tir->list);

	mutex_unlock(&mdev->mlx5e_res.td.list_lock);

	mutex_unlock(&res->td.list_lock);

}



void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
@@ -99,7 +102,7 @@ static int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, 


int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)

{

	struct mlx5e_resources *res = &mdev->mlx5e_res;

	struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;

	int err;



	err = mlx5_core_alloc_pd(mdev, &res->pdn);
@@ -126,8 +129,8 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev) 
		goto err_destroy_mkey;

	}



	INIT_LIST_HEAD(&mdev->mlx5e_res.td.tirs_list);

	mutex_init(&mdev->mlx5e_res.td.list_lock);

	INIT_LIST_HEAD(&res->td.tirs_list);

	mutex_init(&res->td.list_lock);



	return 0;
@@ -142,7 +145,7 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev) 


void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev)

{

	struct mlx5e_resources *res = &mdev->mlx5e_res;

	struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;



	mlx5_free_bfreg(mdev, &res->bfreg);

	mlx5_core_destroy_mkey(mdev, &res->mkey);
@@ -180,8 +183,8 @@ int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, 


	MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);



	mutex_lock(&mdev->mlx5e_res.td.list_lock);

	list_for_each_entry(tir, &mdev->mlx5e_res.td.tirs_list, list) {

	mutex_lock(&mdev->mlx5e_res.hw_objs.td.list_lock);

	list_for_each_entry(tir, &mdev->mlx5e_res.hw_objs.td.tirs_list, list) {

		tirn = tir->tirn;

		err = mlx5_core_modify_tir(mdev, tirn, in);

		if (err)
@@ -192,7 +195,7 @@ int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, 
	kvfree(in);

	if (err)

		netdev_err(priv->netdev, "refresh tir(0x%x) failed, %d\n", tirn, err);

	mutex_unlock(&mdev->mlx5e_res.td.list_lock);

	mutex_unlock(&mdev->mlx5e_res.hw_objs.td.list_lock);



	return err;

}

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+11 −11
Original line number Diff line number Diff line
@@ -302,7 +302,7 @@ static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, 
	MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);

	mlx5e_mkey_set_relaxed_ordering(mdev, mkc);

	MLX5_SET(mkc, mkc, qpn, 0xffffff);

	MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);

	MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);

	MLX5_SET64(mkc, mkc, len, npages << page_shift);

	MLX5_SET(mkc, mkc, translations_octword_size,

		 MLX5_MTT_OCTW(npages));
@@ -1019,7 +1019,7 @@ static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, 
	sq->pdev      = c->pdev;

	sq->mkey_be   = c->mkey_be;

	sq->channel   = c;

	sq->uar_map   = mdev->mlx5e_res.bfreg.map;

	sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;

	sq->min_inline_mode = params->tx_min_inline_mode;

	sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);

	sq->xsk_pool  = xsk_pool;
@@ -1090,7 +1090,7 @@ static int mlx5e_alloc_icosq(struct mlx5e_channel *c, 
	int err;



	sq->channel   = c;

	sq->uar_map   = mdev->mlx5e_res.bfreg.map;

	sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;



	param->wq.db_numa_node = cpu_to_node(c->cpu);

	err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
@@ -1174,7 +1174,7 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, 
	sq->priv      = c->priv;

	sq->ch_ix     = c->ix;

	sq->txq_ix    = txq_ix;

	sq->uar_map   = mdev->mlx5e_res.bfreg.map;

	sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;

	sq->min_inline_mode = params->tx_min_inline_mode;

	sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);

	INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
@@ -1257,7 +1257,7 @@ static int mlx5e_create_sq(struct mlx5_core_dev *mdev, 
	MLX5_SET(sqc,  sqc, flush_in_error_en, 1);



	MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);

	MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);

	MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);

	MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -

					  MLX5_ADAPTER_PAGE_SHIFT);

	MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
@@ -2032,7 +2032,7 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 
	c->cpu      = cpu;

	c->pdev     = mlx5_core_dma_dev(priv->mdev);

	c->netdev   = priv->netdev;

	c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);

	c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);

	c->num_tc   = params->num_tc;

	c->xdp      = !!params->xdp_prog;

	c->stats    = &priv->channel_stats[ix].ch;
@@ -2217,7 +2217,7 @@ void mlx5e_build_rq_param(struct mlx5e_priv *priv, 
	MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);

	MLX5_SET(wq, wq, log_wq_stride,

		 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));

	MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);

	MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.hw_objs.pdn);

	MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);

	MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);

	MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
@@ -2248,7 +2248,7 @@ void mlx5e_build_sq_param_common(struct mlx5e_priv *priv, 
	void *wq = MLX5_ADDR_OF(sqc, sqc, wq);



	MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));

	MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);

	MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.hw_objs.pdn);



	param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(priv->mdev));

}
@@ -3421,10 +3421,10 @@ int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn) 
{

	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);



	MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);

	MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);



	if (MLX5_GET(tisc, tisc, tls_en))

		MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);

		MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);



	if (mlx5_lag_is_lacp_owner(mdev))

		MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
@@ -3494,7 +3494,7 @@ static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) 
static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,

					     u32 rqtn, u32 *tirc)

{

	MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);

	MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.hw_objs.td.tdn);

	MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);

	MLX5_SET(tirc, tirc, indirect_table, rqtn);

	MLX5_SET(tirc, tirc, tunneled_offload_en,