Commit c26de750 authored by Biao Huang's avatar Biao Huang Committed by Jakub Kicinski
Browse files

stmmac: dwmac-mediatek: remove the dwmac_fix_mac_speed 



In current driver, MAC will always enable 2ns delay in RGMII mode,
but that's not the correct usage.

Remove the dwmac_fix_mac_speed() in driver, and recommend "rgmii-id"
for phy-mode in device tree.

Fixes: f2d356a6 ("stmmac: dwmac-mediatek: add support for mt8195")
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarBiao Huang <biao.huang@mediatek.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 50011c32

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

+0 −26
Original line number Diff line number Diff line
@@ -90,7 +90,6 @@ struct mediatek_dwmac_plat_data { 
struct mediatek_dwmac_variant {

	int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);

	int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);

	void (*dwmac_fix_mac_speed)(void *priv, unsigned int speed);



	/* clock ids to be requested */

	const char * const *clk_list;
@@ -443,32 +442,9 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) 
	return 0;

}



static void mt8195_fix_mac_speed(void *priv, unsigned int speed)

{

	struct mediatek_dwmac_plat_data *priv_plat = priv;



	if ((phy_interface_mode_is_rgmii(priv_plat->phy_mode))) {

		/* prefer 2ns fixed delay which is controlled by TXC_PHASE_CTRL,

		 * when link speed is 1Gbps with RGMII interface,

		 * Fall back to delay macro circuit for 10/100Mbps link speed.

		 */

		if (speed == SPEED_1000)

			regmap_update_bits(priv_plat->peri_regmap,

					   MT8195_PERI_ETH_CTRL0,

					   MT8195_RGMII_TXC_PHASE_CTRL |

					   MT8195_DLY_GTXC_ENABLE |

					   MT8195_DLY_GTXC_INV |

					   MT8195_DLY_GTXC_STAGES,

					   MT8195_RGMII_TXC_PHASE_CTRL);

		else

			mt8195_set_delay(priv_plat);

	}

}



static const struct mediatek_dwmac_variant mt8195_gmac_variant = {

	.dwmac_set_phy_interface = mt8195_set_interface,

	.dwmac_set_delay = mt8195_set_delay,

	.dwmac_fix_mac_speed = mt8195_fix_mac_speed,

	.clk_list = mt8195_dwmac_clk_l,

	.num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),

	.dma_bit_mask = 35,
@@ -619,8 +595,6 @@ static int mediatek_dwmac_common_data(struct platform_device *pdev, 
	plat->bsp_priv = priv_plat;

	plat->init = mediatek_dwmac_init;

	plat->clks_config = mediatek_dwmac_clks_config;

	if (priv_plat->variant->dwmac_fix_mac_speed)

		plat->fix_mac_speed = priv_plat->variant->dwmac_fix_mac_speed;



	plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,

					     sizeof(*plat->safety_feat_cfg),