Commit c247c021 authored by Rohit Khaire's avatar Rohit Khaire Committed by Alex Deucher
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drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid 



RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid

Signed-off-by: default avatarRohit Khaire <rohit.khaire@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b71a52f4

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+21 −5
Original line number Diff line number Diff line
@@ -173,6 +173,9 @@ 
#define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030

#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0



#define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5

#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1



#define GFX_RLCG_GC_WRITE_OLD	(0x8 << 28)

#define GFX_RLCG_GC_WRITE	(0x0 << 28)

#define GFX_RLCG_GC_READ	(0x1 << 28)
@@ -1480,8 +1483,15 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32 
		       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;

	scratch_reg3 = adev->rmmio +

		       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;



	if (adev->asic_type >= CHIP_SIENNA_CICHLID) {

		spare_int = adev->rmmio +

			    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]

			     + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;

	} else {

		spare_int = adev->rmmio +

			    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;

	}



	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;

	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
@@ -7349,9 +7359,15 @@ static int gfx_v10_0_hw_fini(void *handle) 
	if (amdgpu_sriov_vf(adev)) {

		gfx_v10_0_cp_gfx_enable(adev, false);

		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */

		if (adev->asic_type >= CHIP_SIENNA_CICHLID) {

			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);

			tmp &= 0xffffff00;

			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);

		} else {

			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

			tmp &= 0xffffff00;

			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);

		}



		return 0;

	}