Unverified Commit c23be918 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "Add non-coherent DMA support for AX45MP" 

Prabhakar <prabhakar.csengg@gmail.com> says:

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

non-coherent DMA support for AX45MP
====================================

On the Andes AX45MP core, cache coherency is a specification option so it
may not be supported. In this case DMA will fail. To get around with this
issue this patch series does the below:

1] Andes alternative ports is implemented as errata which checks if the
IOCP is missing and only then applies to CMO errata. One vendor specific
SBI EXT (ANDES_SBI_EXT_IOCP_SW_WORKAROUND) is implemented as part of
errata.

Below are the configs which Andes port provides (and are selected by
RZ/Five):
      - ERRATA_ANDES
      - ERRATA_ANDES_CMO

OpenSBI patch supporting ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI is now
part v1.3 release.

2] Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
block that allows dynamic adjustment of memory attributes in the runtime.
It contains a configurable amount of PMA entries implemented as CSR
registers to control the attributes of memory locations in interest.
OpenSBI configures the PMA regions as required and creates a reserve memory
node and propagates it to the higher boot stack.

Currently OpenSBI (upstream) configures the required PMA region and passes
this a shared DMA pool to Linux.

    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;

        pma_resv0@58000000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0x58000000 0x0 0x08000000>;
            no-map;
            linux,dma-default;
        };
    };

The above shared DMA pool gets appended to Linux DTB so the DMA memory
requests go through this region.

3] We provide callbacks to synchronize specific content between memory and
cache.

4] RZ/Five SoC selects the below configs
        - AX45MP_L2_CACHE
        - DMA_GLOBAL_POOL
        - ERRATA_ANDES
        - ERRATA_ANDES_CMO

----------x---------------------x--------------------x---------------x----

* b4-shazam-merge:
  soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
  cache: Add L2 cache management for Andes AX45MP RISC-V core
  dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller
  riscv: mm: dma-noncoherent: nonstandard cache operations support
  riscv: errata: Add Andes alternative ports
  riscv: asm: vendorid_list: Add Andes Technology to the vendors list

Link: https://lore.kernel.org/r/20230818135723.80612-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 7f215d00 484861e0

Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright (C) 2023 Renesas Electronics Corp.

%YAML 1.2

---

$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Andestech AX45MP L2 Cache Controller



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  A level-2 cache (L2C) is used to improve the system performance by providing

  a large amount of cache line entries and reasonable access delays. The L2C

  is shared between cores, and a non-inclusive non-exclusive policy is used.



select:

  properties:

    compatible:

      contains:

        enum:

          - andestech,ax45mp-cache



  required:

    - compatible



properties:

  compatible:

    items:

      - const: andestech,ax45mp-cache

      - const: cache



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  cache-line-size:

    const: 64



  cache-level:

    const: 2



  cache-sets:

    const: 1024



  cache-size:

    enum: [131072, 262144, 524288, 1048576, 2097152]



  cache-unified: true



  next-level-cache: true



additionalProperties: false



required:

  - compatible

  - reg

  - interrupts

  - cache-line-size

  - cache-level

  - cache-sets

  - cache-size

  - cache-unified



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    cache-controller@2010000 {

        compatible = "andestech,ax45mp-cache", "cache";

        reg = <0x13400000 0x100000>;

        interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;

        cache-line-size = <64>;

        cache-level = <2>;

        cache-sets = <1024>;

        cache-size = <262144>;

        cache-unified;

    };

MAINTAINERS

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@@ -20340,6 +20340,13 @@ S: Supported 
T:	git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git

F:	drivers/staging/









STANDALONE CACHE CONTROLLER DRIVERS









M:	Conor Dooley <conor@kernel.org>









L:	linux-riscv@lists.infradead.org









S:	Maintained









T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/









F:	drivers/cache

















STARFIRE/DURALAN NETWORK DRIVER









M:	Ion Badulescu <ionut@badula.org>









S:	Odd Fixes

























arch/riscv/Kconfig



+7
−0






























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@@ -275,6 +275,13 @@ config RISCV_DMA_NONCOHERENT







	select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB









	select DMA_DIRECT_REMAP



















config RISCV_NONSTANDARD_CACHE_OPS









	bool









	depends on RISCV_DMA_NONCOHERENT









	help









	  This enables function pointer support for non-standard noncoherent









	  systems to handle cache management.



















config AS_HAS_INSN









	def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)










































arch/riscv/Kconfig.errata



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menu "CPU errata selection"



















config ERRATA_ANDES









	bool "Andes AX45MP errata"









	depends on RISCV_ALTERNATIVE









	help









	  All Andes errata Kconfig depend on this Kconfig. Disabling









	  this Kconfig will disable all Andes errata. Please say "Y"









	  here if your platform uses Andes CPU cores.



















	  Otherwise, please say "N" here to avoid unnecessary overhead.



















config ERRATA_ANDES_CMO









	bool "Apply Andes cache management errata"









	depends on ERRATA_ANDES && MMU && ARCH_R9A07G043









	select RISCV_DMA_NONCOHERENT









	default y









	help









	  This will apply the cache management errata to handle the









	  non-standard handling on non-coherent operations on Andes cores.



















	  If you don't know what to do here, say "Y".



















config ERRATA_SIFIVE









	bool "SiFive errata"









	depends on RISCV_ALTERNATIVE
































arch/riscv/errata/Makefile



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@@ -2,5 +2,6 @@ ifdef CONFIG_RELOCATABLE







KBUILD_CFLAGS += -fno-pie









endif



















obj-$(CONFIG_ERRATA_ANDES) += andes/









obj-$(CONFIG_ERRATA_SIFIVE) += sifive/









obj-$(CONFIG_ERRATA_THEAD) += thead/