Commit c220d08e authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
Browse files

wifi: rtw89: mac: add mac_gen_def::band1_offset to map MAC band1 register address 



There are two copies of MAC hardware called band0 and band1. Basically,
the only difference between them is base address, so we can share functions
with a 'band' (or 'mac_idx') argument.

The offset of base address of WiFi 6 and 7 are 0x2000 and 0x4000
respectively, so add band1_offset field to new introduced struct
mac_gen_def to possibly reuse functions.

Using below spatch script to convert callers:

  @@
  expression reg, band;
  @@
  - rtw89_mac_reg_by_idx(reg, band)
  + rtw89_mac_reg_by_idx(rtwdev, reg, band)

  @@
  expression reg, port, band;
  @@
  - rtw89_mac_reg_by_port(reg, port, band)
  + rtw89_mac_reg_by_port(rtwdev, reg, port, band)

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230822125822.23817-2-pkshih@realtek.com
parent 98fdd77d

drivers/net/wireless/realtek/rtw89/core.c

+2 −2
Original line number Diff line number Diff line
@@ -2504,7 +2504,7 @@ void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 
	rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan);

	rtw89_set_channel(rtwdev);

	rtw89_write32_clr(rtwdev,

			  rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0),

			  rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, RTW89_MAC_0),

			  B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH);



	ieee80211_ready_on_channel(hw);
@@ -2525,7 +2525,7 @@ void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 
	rtw89_leave_lps(rtwdev);



	rtw89_write32_mask(rtwdev,

			   rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0),

			   rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, RTW89_MAC_0),

			   B_AX_RX_FLTR_CFG_MASK,

			   rtwdev->hal.rx_fltr);

drivers/net/wireless/realtek/rtw89/core.h

+2 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 


struct rtw89_dev;

struct rtw89_pci_info;

struct rtw89_mac_gen_def;



extern const struct ieee80211_ops rtw89_ops;
@@ -3435,6 +3436,7 @@ struct rtw89_chip_info { 
	enum rtw89_core_chip_id chip_id;

	enum rtw89_chip_gen chip_gen;

	const struct rtw89_chip_ops *ops;

	const struct rtw89_mac_gen_def *mac_def;

	const char *fw_basename;

	u8 fw_format_max;

	bool try_ce_fw;

drivers/net/wireless/realtek/rtw89/fw.c

+2 −2
Original line number Diff line number Diff line
@@ -3885,7 +3885,7 @@ void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 
	rx_fltr &= ~B_AX_A_BC;

	rx_fltr &= ~B_AX_A_A1_MATCH;

	rtw89_write32_mask(rtwdev,

			   rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0),

			   rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, RTW89_MAC_0),

			   B_AX_RX_FLTR_CFG_MASK,

			   rx_fltr);

}
@@ -3903,7 +3903,7 @@ void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 
		return;



	rtw89_write32_mask(rtwdev,

			   rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0),

			   rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, RTW89_MAC_0),

			   B_AX_RX_FLTR_CFG_MASK,

			   rtwdev->hal.rx_fltr);

drivers/net/wireless/realtek/rtw89/mac.c

+89 −82
Original line number Diff line number Diff line
@@ -2082,7 +2082,7 @@ static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	if (ret)

		return ret;



	reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx);



	val = rtw89_read32(rtwdev, reg);

	val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) |
@@ -2109,7 +2109,7 @@ static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	if (ret)

		return ret;



	reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx);

	if (rtwdev->chip->chip_id == RTL8852C)

		rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,

				   SIFS_MACTXEN_T1_V1);
@@ -2118,14 +2118,14 @@ static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
				   SIFS_MACTXEN_T1);



	if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) {

		reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx);

		rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);

	}



	reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx);

	rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN);



	reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx);

	if (rtwdev->chip->chip_id == RTL8852C) {

		val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,

					B_AX_TX_PARTIAL_MODE);
@@ -2165,13 +2165,13 @@ int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 


	switch (type) {

	case RTW89_MGNT:

		reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx);

		break;

	case RTW89_CTRL:

		reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx);

		break;

	case RTW89_DATA:

		reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx);

		break;

	default:

		rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
@@ -2202,9 +2202,9 @@ static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
		    B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK |

		    B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK |

		    B_AX_HE_SIGB_CRC_CHK;

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx),

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx),

		      mac_ftlr);

	rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx),

	rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx),

		      plcp_ftlr);



	return 0;
@@ -2224,20 +2224,20 @@ static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 
	switch (rtwdev->chip->chip_id) {

	case RTL8852A:

	case RTL8852B:

		reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx);

		val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav;

		rtw89_write32(rtwdev, reg, val32);



		reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);

		val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca;

		rtw89_write32(rtwdev, reg, val32);

		break;

	default:

		reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx);

		val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav;

		rtw89_write32(rtwdev, reg, val32);



		reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);

		val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca;

		rtw89_write32(rtwdev, reg, val32);

		break;
@@ -2253,7 +2253,7 @@ static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	if (ret)

		return ret;



	reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx);

	val = rtw89_read32(rtwdev, reg);

	val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA |

		B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 |
@@ -2294,7 +2294,7 @@ static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);

	if (ret)

		return ret;

	reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx);

	rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN);



	return 0;
@@ -2309,13 +2309,13 @@ static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	if (ret)

		return ret;



	reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx);

	rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN);



	reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx);

	rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD);



	reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx);

	rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE);

	rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE);
@@ -2333,7 +2333,7 @@ static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	if (ret)

		return ret;



	reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);

	val = rtw89_read32(rtwdev, reg);

	val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK;

	val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK);
@@ -2353,12 +2353,12 @@ static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs);

	rtw89_write32(rtwdev, reg, val);



	reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx);

	rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);



	reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx);

	rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);

	reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx);

	rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);



	return 0;
@@ -2397,10 +2397,10 @@ static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	if (mac_idx == RTW89_MAC_0)

		rst_bacam(rtwdev);



	reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx);

	rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL);



	reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx);

	val = rtw89_read16(rtwdev, reg);

	val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO,

			       B_AX_RX_DLK_DATA_TIME_MASK);
@@ -2408,10 +2408,10 @@ static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
			       B_AX_RX_DLK_CCA_TIME_MASK);

	rtw89_write16(rtwdev, reg, val);



	reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx);

	rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1);



	reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx);

	if (mac_idx == RTW89_MAC_0)

		rx_qta = rtwdev->mac.dle_info.c0_rx_qta;

	else
@@ -2425,13 +2425,13 @@ static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	if (rtwdev->chip->chip_id == RTL8852A &&

	    rtwdev->hal.cv == CHIP_CBV) {

		rtw89_write16_mask(rtwdev,

				   rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx),

				   rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx),

				   B_AX_RX_DLK_CCA_TIME_MASK, 0);

		rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx),

		rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx),

				  BIT(12));

	}



	reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx);

	rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK);



	return ret;
@@ -2447,7 +2447,7 @@ static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	if (ret)

		return ret;



	reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);

	val = rtw89_read32(rtwdev, reg);

	val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK);

	val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK);
@@ -2455,7 +2455,7 @@ static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	rtw89_write32(rtwdev, reg, val);



	if (chip_id == RTL8852A || chip_id == RTL8852B) {

		reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx);

		rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);

	}
@@ -2485,7 +2485,7 @@ static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
		return ret;



	if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {

		reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx);

		val = rtw89_read32(rtwdev, reg);

		val = u32_replace_bits(val, S_AX_CTS2S_TH_1K,

				       B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK);
@@ -2494,7 +2494,7 @@ static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
		val |= B_AX_HW_CTS2SELF_EN;

		rtw89_write32(rtwdev, reg, val);



		reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx);

		val = rtw89_read32(rtwdev, reg);

		val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK);

		val &= ~B_AX_PTCL_TX_ARB_TO_MODE;
@@ -2531,7 +2531,7 @@ static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 
	if (ret)

		return ret;



	reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx);

	rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE);



	return 0;
@@ -2725,7 +2725,7 @@ static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 
static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx,

				  u16 tx_en, u16 tx_en_mask)

{

	u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx);

	u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx);

	u16 val;

	int ret;
@@ -2747,7 +2747,7 @@ static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 
static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx,

				     u32 tx_en, u32 tx_en_mask)

{

	u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx);

	u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx);

	u32 val;

	int ret;
@@ -2768,7 +2768,7 @@ int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 
	int ret;



	*tx_en = rtw89_read16(rtwdev,

			      rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx));

			      rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx));



	switch (sel) {

	case RTW89_SCH_TX_SEL_ALL:
@@ -2809,7 +2809,7 @@ int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 
	int ret;



	*tx_en = rtw89_read32(rtwdev,

			      rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx));

			      rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx));



	switch (sel) {

	case RTW89_SCH_TX_SEL_ALL:
@@ -3016,7 +3016,7 @@ static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 
	if (ret)

		return ret;



	reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx);



	ret = read_poll_timeout(rtw89_read8, val,

				(val & B_AX_PTCL_TX_ON_STAT) == 0,
@@ -3224,7 +3224,7 @@ static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 
{

	u32 reg;



	reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx);

	rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN |

				       B_AX_FSM_TIMEOUT_ERR_INT_EN);

	rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN);
@@ -3235,7 +3235,7 @@ static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 
	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;

	u32 reg;



	reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx);

	rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);

	rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);

}
@@ -3246,12 +3246,12 @@ static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 
	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;

	u32 reg;



	reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx);

	rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);

	rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);



	if (chip_id == RTL8852C) {

		reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx);

		rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);

		rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);

	}
@@ -3262,7 +3262,7 @@ static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 
	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;

	u32 reg;



	reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx);

	rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);

	rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);

}
@@ -3272,7 +3272,7 @@ static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 
	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;

	u32 reg;



	reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx);

	rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);

	rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);

}
@@ -3282,7 +3282,7 @@ static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 
	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;

	u32 reg;



	reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx);

	rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);

	rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);

}
@@ -3860,7 +3860,7 @@ static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 
	u8 port = rtwvif->port;

	u32 reg;



	reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, hiq_win_addr[port], rtwvif->mac_idx);

	rtw89_write8(rtwdev, reg, win);

}
@@ -3871,7 +3871,7 @@ static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 
	const struct rtw89_port_reg *p = &rtw_port_base;

	u32 addr;



	addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx);

	addr = rtw89_mac_reg_by_idx(rtwdev, R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx);

	rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE);



	rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,
@@ -3930,7 +3930,7 @@ static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 


	bss_color = vif->bss_conf.he_bss_color.color;

	reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0;

	reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx);

	rtw89_write32_mask(rtwdev, reg, masks[port], bss_color);

}
@@ -3944,7 +3944,7 @@ static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 
		return;



	if (port == 0) {

		reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MBSSID_CTRL, rtwvif->mac_idx);

		rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK);

	}

}
@@ -3956,7 +3956,7 @@ static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 
	u32 reg;

	u32 val;



	reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MBSSID_DROP_0, rtwvif->mac_idx);

	val = rtw89_read32(rtwdev, reg);

	val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port));

	if (port == 0)
@@ -4014,7 +4014,7 @@ void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 
	u32 val, reg;



	val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu);

	reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4,

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PORT0_TSF_SYNC + rtwvif->port * 4,

				   rtwvif->mac_idx);



	rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port);
@@ -4204,7 +4204,7 @@ void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 
			  rtw89_mac_check_he_obss_narrow_bw_ru_iter,

			  &tolerated);



	reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx);

	if (tolerated)

		rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);

	else
@@ -4731,7 +4731,7 @@ bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 
{

	const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem;

	enum rtw89_qta_mode mode = dle_mem->mode;

	u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx);

	u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);



	if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) {

		rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n",
@@ -4760,7 +4760,7 @@ EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 


int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)

{

	u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx);

	u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx);

	int ret;



	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
@@ -4807,7 +4807,7 @@ void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 
	time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX);

	len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX);



	reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_HT_0, mac_idx);

	rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th);

	rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th);

}
@@ -5043,7 +5043,7 @@ int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 
	if (ret)

		return ret;



	reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band);

	val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) |

	      (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) |

	      (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) |
@@ -5133,7 +5133,7 @@ u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 
	u32 reg;

	u16 cnt;



	reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band);

	cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK);

	rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST);
@@ -5146,7 +5146,7 @@ static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 
	u32 reg;



	rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep);

	reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);

	if (keep) {

		set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);

		rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
@@ -5165,7 +5165,7 @@ static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 
		   B_AX_BFMEE_HE_NDPA_EN;



	rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en);

	reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);

	if (en) {

		set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);

		rtw89_write32_set(rtwdev, reg, mask);
@@ -5187,30 +5187,30 @@ static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 


	/* AP mode set tx gid to 63 */

	/* STA mode set tx gid to 0(default) */

	reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx);

	rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN);



	reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx);

	rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP);



	reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);

	val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER);

	rtw89_write32(rtwdev, reg, val32);

	rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true);

	rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);



	reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);

	rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL |

				       B_AX_BFMEE_USE_NSTS |

				       B_AX_BFMEE_CSI_GID_SEL |

				       B_AX_BFMEE_CSI_FORCE_RETE_EN);

	reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx);

	rtw89_write32(rtwdev, reg,

		      u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) |

		      u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) |

		      u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK));



	reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx);

	rtw89_write32_set(rtwdev, reg,

			  B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN);
@@ -5254,7 +5254,7 @@ static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 
	nc = min(nc, sound_dim);

	nr = min(nr, sound_dim);



	reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);

	rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);



	val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) |
@@ -5266,9 +5266,9 @@ static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 
	      FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en);



	if (port_sel == 0)

		reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);

	else

		reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);



	rtw89_write16(rtwdev, reg, val);
@@ -5304,11 +5304,11 @@ static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 
			 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) |

			 BIT(RTW89_MAC_BF_RRSC_HT_MSC5));

	}

	reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);

	rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);

	rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN);

	rtw89_write32(rtwdev,

		      rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx),

		      rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx),

		      rrsc);



	return 0;
@@ -5346,19 +5346,21 @@ void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif * 
	rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n");



	p = (__le32 *)conf->mu_group.membership;

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx),

	rtw89_write32(rtwdev,

		      rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx),

		      le32_to_cpu(p[0]));

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx),

	rtw89_write32(rtwdev,

		      rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx),

		      le32_to_cpu(p[1]));



	p = (__le32 *)conf->mu_group.position;

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx),

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx),

		      le32_to_cpu(p[0]));

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx),

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx),

		      le32_to_cpu(p[1]));

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx),

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx),

		      le32_to_cpu(p[2]));

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx),

	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx),

		      le32_to_cpu(p[3]));

}
@@ -5449,7 +5451,7 @@ __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 
			return ret;

		}



		reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx);

		rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK,

				   max_tx_time >> 5);

	}
@@ -5489,7 +5491,7 @@ int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 
			return ret;

		}



		reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx);

		*tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5;

	}
@@ -5531,7 +5533,7 @@ int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 
			return ret;

		}



		reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx);

		reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx);

		*tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK);

	}
@@ -5550,7 +5552,7 @@ int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 
	if (ret)

		return ret;



	reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx);

	reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MUEDCA_EN, mac_idx);

	if (en)

		rtw89_write16_set(rtwdev, reg, set);

	else
@@ -5673,3 +5675,8 @@ int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 
	}

	return ret;

}



const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {

	.band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET,

};

EXPORT_SYMBOL(rtw89_mac_gen_ax);

drivers/net/wireless/realtek/rtw89/mac.h

+24 −12

File changed.

Preview size limit exceeded, changes collapsed.