Commit c1f9f10a authored by Kai Ye's avatar Kai Ye Committed by Zheng Zengkai
Browse files

crypto: hisilicon/sec - fix the CTR mode BD configuration 

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I4750I?from=project-issue



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The CTR counter is 32bit rollover default on the BD.
But the NIST standard is 128bit rollover. it cause the
testing failed, so need to fix the BD configuration.

Signed-off-by: default avatarKai Ye <yekai13@huawei.com>
Reviewed-by: default avatarHao Fang <fanghao11@huawei.com>
Reviewed-by: default avatarMingqiang Ling <lingmingqiang@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 465c9615

drivers/crypto/hisilicon/sec2/sec_crypto.c

+6 −0
Original line number Diff line number Diff line
@@ -42,6 +42,8 @@ 
#define SEC_DE_OFFSET_V3		9

#define SEC_SCENE_OFFSET_V3	5

#define SEC_CKEY_OFFSET_V3	13

#define SEC_CTR_CNT_OFFSET	25

#define SEC_CTR_CNT_ROLLOVER	2

#define SEC_SRC_SGL_OFFSET_V3	11

#define SEC_DST_SGL_OFFSET_V3	14

#define SEC_CALG_OFFSET_V3	4
@@ -1301,6 +1303,10 @@ static int sec_skcipher_bd_fill_v3(struct sec_ctx *ctx, struct sec_req *req) 
		cipher = SEC_CIPHER_DEC;

	sec_sqe3->c_icv_key |= cpu_to_le16(cipher);



	/* Set the CTR counter mode is 128bit rollover */

	sec_sqe3->auth_mac_key = cpu_to_le32((u32)SEC_CTR_CNT_ROLLOVER <<

					SEC_CTR_CNT_OFFSET);



	if (req->use_pbuf) {

		bd_param |= SEC_PBUF << SEC_SRC_SGL_OFFSET_V3;

		bd_param |= SEC_PBUF << SEC_DST_SGL_OFFSET_V3;

drivers/crypto/hisilicon/sec2/sec_crypto.h

+4 −2
Original line number Diff line number Diff line
@@ -354,8 +354,10 @@ struct sec_sqe3 { 
	 * akey_len: 9~14 bits

	 * a_alg: 15~20 bits

	 * key_sel: 21~24 bits

	 * updata_key: 25 bits

	 * reserved: 26~31 bits

	 * ctr_count_mode/sm4_xts: 25~26 bits

	 * sva_prefetch: 27 bits

	 * key_wrap_num: 28~30 bits

	 * update_key: 31 bits

	 */

	__le32 auth_mac_key;

	__le32 salt;