Commit c1f6b45e authored by 周琰杰 (Zhou Yanjie)'s avatar 周琰杰 (Zhou Yanjie) Committed by Thomas Bogendoerfer
Browse files

MIPS: Ingenic: Add CPU nodes for Ingenic SoCs. 



Add 'cpus' node to the jz4725b.dtsi, jz4740.dtsi, jz4770.dtsi,
jz4780.dtsi, x1000.dtsi, and x1830.dtsi files.

Tested-by: default avatarH. Nikolaus Schaller <hns@goldelico.com>
Tested-by: default avatarPaul Boddie <paul@boddie.org.uk>
Signed-off-by: default avatar周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: default avatarPaul Cercueil <paul@crapouillou.net>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 307c9926

arch/mips/boot/dts/ingenic/jz4725b.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -7,6 +7,20 @@ 
	#size-cells = <1>;

	compatible = "ingenic,jz4725b";



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "ingenic,xburst-mxu1.0";

			reg = <0>;



			clocks = <&cgu JZ4725B_CLK_CCLK>;

			clock-names = "cpu";

		};

	};



	cpuintc: interrupt-controller {

		#address-cells = <0>;

		#interrupt-cells = <1>;

arch/mips/boot/dts/ingenic/jz4740.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -7,6 +7,20 @@ 
	#size-cells = <1>;

	compatible = "ingenic,jz4740";



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "ingenic,xburst-mxu1.0";

			reg = <0>;



			clocks = <&cgu JZ4740_CLK_CCLK>;

			clock-names = "cpu";

		};

	};



	cpuintc: interrupt-controller {

		#address-cells = <0>;

		#interrupt-cells = <1>;

arch/mips/boot/dts/ingenic/jz4770.dtsi

+14 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0



#include <dt-bindings/clock/jz4770-cgu.h>

#include <dt-bindings/clock/ingenic,tcu.h>
@@ -8,6 +7,20 @@ 
	#size-cells = <1>;

	compatible = "ingenic,jz4770";



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "ingenic,xburst-fpu1.0-mxu1.1";

			reg = <0>;



			clocks = <&cgu JZ4770_CLK_CCLK>;

			clock-names = "cpu";

		};

	};



	cpuintc: interrupt-controller {

		#address-cells = <0>;

		#interrupt-cells = <1>;

arch/mips/boot/dts/ingenic/jz4780.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -8,6 +8,29 @@ 
	#size-cells = <1>;

	compatible = "ingenic,jz4780";



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "ingenic,xburst-fpu1.0-mxu1.1";

			reg = <0>;



			clocks = <&cgu JZ4780_CLK_CPU>;

			clock-names = "cpu";

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "ingenic,xburst-fpu1.0-mxu1.1";

			reg = <1>;



			clocks = <&cgu JZ4780_CLK_CORE1>;

			clock-names = "cpu";

		};

	};



	cpuintc: interrupt-controller {

		#address-cells = <0>;

		#interrupt-cells = <1>;

arch/mips/boot/dts/ingenic/x1000.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -8,6 +8,20 @@ 
	#size-cells = <1>;

	compatible = "ingenic,x1000", "ingenic,x1000e";



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "ingenic,xburst-fpu1.0-mxu1.1";

			reg = <0>;



			clocks = <&cgu X1000_CLK_CPU>;

			clock-names = "cpu";

		};

	};



	cpuintc: interrupt-controller {

		#address-cells = <0>;

		#interrupt-cells = <1>;