Commit c1e846b8 authored by Rajan Vaja's avatar Rajan Vaja Committed by Stephen Boyd
Browse files

clk: zynqmp: Extend driver for versal 



Add Versal compatible string to support Versal
binding.

Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Link: https://lkml.kernel.org/r/1575527759-26452-3-git-send-email-rajan.vaja@xilinx.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 35254680

drivers/clk/zynqmp/clkc.c

+2 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * Zynq UltraScale+ MPSoC clock controller

 *

 *  Copyright (C) 2016-2018 Xilinx

 *  Copyright (C) 2016-2019 Xilinx

 *

 * Based on drivers/clk/zynq/clkc.c

 */
@@ -749,6 +749,7 @@ static int zynqmp_clock_probe(struct platform_device *pdev) 


static const struct of_device_id zynqmp_clock_of_match[] = {

	{.compatible = "xlnx,zynqmp-clk"},

	{.compatible = "xlnx,versal-clk"},

	{},

};

MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);