Commit c18773d1 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sc8280xp: add SoundWire and LPASS 



Add LPASS Codecs along with SoundWire controller for TX, RX, WSA and VA macros
along with LPASS LPI pinctrl node.

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221123104342.26140-3-srinivas.kandagatla@linaro.org
parent e73defb2

arch/arm64/boot/dts/qcom/sc8280xp.dtsi

+320 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <dt-bindings/power/qcom-rpmpd.h>

#include <dt-bindings/soc/qcom,gpr.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>

#include <dt-bindings/sound/qcom,q6afe.h>

#include <dt-bindings/thermal/thermal.h>



/ {
@@ -1712,6 +1713,322 @@ 
			};

		};



		rxmacro: rxmacro@3200000 {

			compatible = "qcom,sc8280xp-lpass-rx-macro";

			reg = <0 0x03200000 0 0x1000>;

			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&vamacro>;

			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";

			assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

					  <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			assigned-clock-rates = <19200000>, <19200000>;



			clock-output-names = "mclk";

			#clock-cells = <0>;

			#sound-dai-cells = <1>;



			pinctrl-names = "default";

			pinctrl-0 = <&rx_swr_default>;

		};



		/* RX */

		swr1: soundwire-controller@3210000 {

			compatible = "qcom,soundwire-v1.6.0";

			reg = <0 0x03210000 0 0x2000>;

			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rxmacro>;

			clock-names = "iface";

			label = "RX";



			qcom,din-ports = <0>;

			qcom,dout-ports = <5>;



			qcom,ports-sinterval-low =	/bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;

			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;

			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;

			qcom,ports-hstart =		/bits/ 8 <0xff 0x03 0xff 0xff 0xff>;

			qcom,ports-hstop =		/bits/ 8 <0xff 0x06 0xff 0xff 0xff>;

			qcom,ports-word-length =	/bits/ 8 <0x01 0x07 0x04 0xff 0xff>;

			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0x00 0x01 0xff 0xff>;

			qcom,ports-lane-control =	/bits/ 8 <0x01 0x00 0x00 0x00 0x00>;

			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0x00>;



			#sound-dai-cells = <1>;

			#address-cells = <2>;

			#size-cells = <0>;

		};



		txmacro: txmacro@3220000 {

			compatible = "qcom,sc8280xp-lpass-tx-macro";

			reg = <0 0x03220000 0 0x1000>;

			pinctrl-names = "default";

			pinctrl-0 = <&tx_swr_default>;

			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&vamacro>;



			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";

			assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

					  <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			assigned-clock-rates = <19200000>, <19200000>;

			clock-output-names = "mclk";



			#clock-cells = <0>;

			#address-cells = <2>;

			#size-cells = <2>;

			#sound-dai-cells = <1>;

		};



		wsamacro: codec@3240000 {

			compatible = "qcom,sc8280xp-lpass-wsa-macro";

			reg = <0 0x03240000 0 0x1000>;

			clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&vamacro>;

			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";

			assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

					  <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			assigned-clock-rates = <19200000>, <19200000>;



			#clock-cells = <0>;

			clock-output-names = "mclk";

			#sound-dai-cells = <1>;



			pinctrl-names = "default";

			pinctrl-0 = <&wsa_swr_default>;

		};



		/* WSA */

		swr0: soundwire-controller@3250000 {

			reg = <0 0x03250000 0 0x2000>;

			compatible = "qcom,soundwire-v1.6.0";

			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&wsamacro>;

			clock-names = "iface";



			qcom,din-ports = <2>;

			qcom,dout-ports = <6>;



			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;

			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;

			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;

			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;

			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;



			#sound-dai-cells = <1>;

			#address-cells = <2>;

			#size-cells = <0>;

		};



		/* TX */

		swr2: soundwire-controller@3330000 {

			compatible = "qcom,soundwire-v1.6.0";

			reg = <0 0x03330000 0 0x2000>;

			interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,

					      <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "core", "wake";



			clocks = <&vamacro>;

			clock-names = "iface";

			label = "TX";

			#sound-dai-cells = <1>;

			#address-cells = <2>;

			#size-cells = <0>;



			qcom,din-ports = <4>;

			qcom,dout-ports = <0>;

			qcom,ports-sinterval-low =	/bits/ 8 <0x01 0x03 0x03 0x03>;

			qcom,ports-offset1 =		/bits/ 8 <0x01 0x00 0x02 0x01>;

			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x00 0x00>;

			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0xff 0xff>;

			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff>;

			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff>;

			qcom,ports-word-length =	/bits/ 8 <0xff 0x00 0xff 0xff>;

			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff>;

			qcom,ports-lane-control =	/bits/ 8 <0x00 0x01 0x00 0x00>;

		};



		vamacro: codec@3370000 {

			compatible = "qcom,sc8280xp-lpass-va-macro";

			reg = <0 0x03370000 0 0x1000>;

			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			clock-names = "mclk", "macro", "dcodec", "npl";

			assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			assigned-clock-rates = <19200000>;



			#clock-cells = <0>;

			clock-output-names = "fsgen";

			#sound-dai-cells = <1>;

		};



		lpass_tlmm: pinctrl@33c0000 {

			compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";

			reg = <0 0x33c0000 0x0 0x20000>,

			      <0 0x3550000 0x0 0x10000>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&lpass_tlmm 0 0 18>;



			clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

			clock-names = "core", "audio";



			tx_swr_default: tx-swr-default-state {

				clk-pins {

					pins = "gpio0";

					function = "swr_tx_clk";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-disable;

				};



				data-pins {

					pins = "gpio1", "gpio2";

					function = "swr_tx_data";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-bus-hold;

				};

			};



			rx_swr_default: rx-swr-default-state {

				clk-pins {

					pins = "gpio3";

					function = "swr_rx_clk";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-disable;

				};



				data-pins {

					pins = "gpio4", "gpio5";

					function = "swr_rx_data";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-bus-hold;

				};

			};



			dmic01_default: dmic01-default-state {

				clk-pins {

					pins = "gpio6";

					function = "dmic1_clk";

					drive-strength = <8>;

					output-high;

				};



				data-pins {

					pins = "gpio7";

					function = "dmic1_data";

					drive-strength = <8>;

					input-enable;

				};

			};



			dmic01_sleep: dmic01-sleep-state {

				clk-pins {

					pins = "gpio6";

					function = "dmic1_clk";

					drive-strength = <2>;

					bias-disable;

					output-low;

				};



				data-pins {

					pins = "gpio7";

					function = "dmic1_data";

					drive-strength = <2>;

					bias-pull-down;

					input-enable;

				};

			};



			dmic02_default: dmic02-default-state {

				clk-pins {

					pins = "gpio8";

					function = "dmic2_clk";

					drive-strength = <8>;

					output-high;

				};



				data-pins {

					pins = "gpio9";

					function = "dmic2_data";

					drive-strength = <8>;

					input-enable;

				};

			};



			dmic02_sleep: dmic02-sleep-state {

				clk-pins {

					pins = "gpio8";

					function = "dmic2_clk";

					drive-strength = <2>;

					bias-disable;

					output-low;

				};



				data-pins {

					pins = "gpio9";

					function = "dmic2_data";

					drive-strength = <2>;

					bias-pull-down;

					input-enable;

				};

			};



			wsa_swr_default: wsa-swr-default-state {

				clk-pins {

					pins = "gpio10";

					function = "wsa_swr_clk";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-disable;

				};



				data-pins {

					pins = "gpio11";

					function = "wsa_swr_data";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-bus-hold;



				};

			};



			wsa2_swr_default: wsa2-swr-default-state {

				clk-pins {

					pins = "gpio15";

					function = "wsa2_swr_clk";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-disable;

				};



				data-pins {

					pins = "gpio16";

					function = "wsa2_swr_data";

					drive-strength = <2>;

					slew-rate = <1>;

					bias-bus-hold;

				};

			};

		};



		usb_0_qmpphy: phy-wrapper@88ec000 {

			compatible = "qcom,sc8280xp-qmp-usb43dp-phy";

			reg = <0 0x088ec000 0 0x1e4>,
@@ -2632,6 +2949,9 @@ 
		};

	};



	sound: sound {

	};



	thermal-zones {

		cpu0-thermal {

			polling-delay-passive = <250>;