Commit c1143ca2 authored by Cruise Hung's avatar Cruise Hung Committed by Alex Deucher
Browse files

drm/amd/display: Fix DP MST timeslot issue when fallback happened 



[Why]
When USB4 DP link training failed and fell back to lower link rate,
the time slot calculation uses the verified_link_cap.
And the verified_link_cap was not updated to the new one.
It caused the wrong VC payload time-slot was allocated.

[How]
Updated verified_link_cap with the new one from cur_link_settings
after the LT completes successfully.

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarCruise Hung <Cruise.Hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent abffd871

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+7 −1
Original line number Diff line number Diff line
@@ -2758,8 +2758,14 @@ bool perform_link_training_with_retries( 
						skip_video_pattern);



				/* Transmit idle pattern once training successful. */

				if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low)

				if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) {

					dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);

					/* Update verified link settings to current one

					 * Because DPIA LT might fallback to lower link setting.

					 */

					link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;

					link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;

				}

			} else {

				status = dc_link_dp_perform_link_training(link,

						&pipe_ctx->link_res,