Commit c1001a62 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v5.17-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull an Amlogic clock driver update from Jerome Brunet:

 - Fix MPLL0 gxbb SDM enable

* tag 'clk-meson-v5.17-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB
parents fa55b7dc ff54938d

drivers/clk/meson/gxbb.c

+41 −3
Original line number Diff line number Diff line
@@ -713,6 +713,35 @@ static struct clk_regmap gxbb_mpll_prediv = { 
};



static struct clk_regmap gxbb_mpll0_div = {

	.data = &(struct meson_clk_mpll_data){

		.sdm = {

			.reg_off = HHI_MPLL_CNTL7,

			.shift   = 0,

			.width   = 14,

		},

		.sdm_en = {

			.reg_off = HHI_MPLL_CNTL,

			.shift   = 25,

			.width	 = 1,

		},

		.n2 = {

			.reg_off = HHI_MPLL_CNTL7,

			.shift   = 16,

			.width   = 9,

		},

		.lock = &meson_clk_lock,

	},

	.hw.init = &(struct clk_init_data){

		.name = "mpll0_div",

		.ops = &meson_clk_mpll_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&gxbb_mpll_prediv.hw

		},

		.num_parents = 1,

	},

};



static struct clk_regmap gxl_mpll0_div = {

	.data = &(struct meson_clk_mpll_data){

		.sdm = {

			.reg_off = HHI_MPLL_CNTL7,
@@ -749,7 +778,16 @@ static struct clk_regmap gxbb_mpll0 = { 
	.hw.init = &(struct clk_init_data){

		.name = "mpll0",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw },

		.parent_data = &(const struct clk_parent_data) {

			/*

			 * Note:

			 * GXL and GXBB have different SDM_EN registers. We

			 * fallback to the global naming string mechanism so

			 * mpll0_div picks up the appropriate one.

			 */

			.name = "mpll0_div",

			.index = -1,

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},
@@ -3044,7 +3082,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = { 
		[CLKID_VAPB_1]		    = &gxbb_vapb_1.hw,

		[CLKID_VAPB_SEL]	    = &gxbb_vapb_sel.hw,

		[CLKID_VAPB]		    = &gxbb_vapb.hw,

		[CLKID_MPLL0_DIV]	    = &gxbb_mpll0_div.hw,

		[CLKID_MPLL0_DIV]	    = &gxl_mpll0_div.hw,

		[CLKID_MPLL1_DIV]	    = &gxbb_mpll1_div.hw,

		[CLKID_MPLL2_DIV]	    = &gxbb_mpll2_div.hw,

		[CLKID_MPLL_PREDIV]	    = &gxbb_mpll_prediv.hw,
@@ -3439,7 +3477,7 @@ static struct clk_regmap *const gxl_clk_regmaps[] = { 
	&gxbb_mpll0,

	&gxbb_mpll1,

	&gxbb_mpll2,

	&gxbb_mpll0_div,

	&gxl_mpll0_div,

	&gxbb_mpll1_div,

	&gxbb_mpll2_div,

	&gxbb_cts_amclk_div,