Commit c0e6265e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "A semi-large pile of clk driver fixes this time around.

  Nothing is touching the core so these fixes are fairly well contained
  to specific devices that use these clk drivers.

   - Some Allwinner SoC fixes to gracefully handle errors and mark an
     RTC clk as critical so that the RTC keeps ticking.

   - Fix AXI bus clks and RTC clk design for Microchip PolarFire SoC
     driver introduced this cycle. This has some devicetree bits acked
     by riscv maintainers. We're fixing it now so that the prior
     bindings aren't released in a major kernel version.

   - Remove a reset on Microchip PolarFire SoCs that broke when enabling
     CONFIG_PM.

   - Set a min/max for the Qualcomm graphics clk. This got broken by the
     clk rate range patches introduced this cycle"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: sunxi: sun9i-mmc: check return value after calling platform_get_resource()
  clk: sunxi-ng: sun6i-rtc: Mark rtc-32k as critical
  riscv: dts: microchip: reparent mpfs clocks
  clk: microchip: mpfs: add RTCREF clock control
  clk: microchip: mpfs: re-parent the configurable clocks
  dt-bindings: rtc: add refclk to mpfs-rtc
  dt-bindings: clk: mpfs: add defines for two new clocks
  dt-bindings: clk: mpfs document msspll dri registers
  riscv: dts: microchip: fix usage of fic clocks on mpfs
  clk: microchip: mpfs: mark CLK_ATHENA as critical
  clk: microchip: mpfs: fix parents for FIC clocks
  clk: qcom: clk-rcg2: fix gfx3d frequency calculation
  clk: microchip: mpfs: don't reset disabled peripherals
  clk: sunxi-ng: fix not NULL terminated coccicheck error
parents bd3d3ade a91b05f6

Documentation/devicetree/bindings/clock/microchip,mpfs.yaml

+11 −2
Original line number Diff line number Diff line
@@ -22,7 +22,16 @@ properties: 
    const: microchip,mpfs-clkcfg



  reg:

    maxItems: 1

    items:

      - description: |

          clock config registers:

          These registers contain enable, reset & divider tables for the, cpu,

          axi, ahb and rtc/mtimer reference clocks as well as enable and reset

          for the peripheral clocks.

      - description: |

          mss pll dri registers:

          Block of registers responsible for dynamic reconfiguration of the mss

          pll



  clocks:

    maxItems: 1
@@ -51,7 +60,7 @@ examples: 
            #size-cells = <2>;

            clkcfg: clock-controller@20002000 {

                compatible = "microchip,mpfs-clkcfg";

                reg = <0x0 0x20002000 0x0 0x1000>;

                reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;

                clocks = <&ref>;

                #clock-cells = <1>;

        };

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

+12 −3
Original line number Diff line number Diff line
@@ -31,11 +31,19 @@ properties: 
          to that of the RTC's count register.



  clocks:

    maxItems: 1

    items:

      - description: |

          AHB clock

      - description: |

          Reference clock: divided by the prescaler to create a time-based

          strobe (typically 1 Hz) for the calendar counter. By default, the rtc

          on the PolarFire SoC shares it's reference with MTIMER so this will

          be a 1 MHz clock.



  clock-names:

    items:

      - const: rtc

      - const: rtcref



required:

  - compatible
@@ -48,11 +56,12 @@ additionalProperties: false 


examples:

  - |

    #include "dt-bindings/clock/microchip,mpfs-clock.h"

    rtc@20124000 {

        compatible = "microchip,mpfs-rtc";

        reg = <0x20124000 0x1000>;

        clocks = <&clkcfg 21>;

        clock-names = "rtc";

        clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;

        clock-names = "rtc", "rtcref";

        interrupts = <80>, <81>;

    };

...

arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi

+14 −2
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
		reg = <0x0 0x41000000 0x0 0xF0>;

		microchip,sync-update-mask = /bits/ 32 <0>;

		#pwm-cells = <2>;

		clocks = <&clkcfg CLK_FIC3>;

		clocks = <&fabric_clk3>;

		status = "disabled";

	};
@@ -16,10 +16,22 @@ 
		reg = <0x0 0x44000000 0x0 0x1000>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&clkcfg CLK_FIC3>;

		clocks = <&fabric_clk3>;

		interrupt-parent = <&plic>;

		interrupts = <122>;

		clock-frequency = <100000>;

		status = "disabled";

	};



	fabric_clk3: fabric-clk3 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <62500000>;

	};



	fabric_clk1: fabric-clk1 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <125000000>;

	};

};

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ 
};



&refclk {

	clock-frequency = <600000000>;

	clock-frequency = <125000000>;

};



&mmuart1 {

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -141,7 +141,7 @@ 
		};

	};



	refclk: msspllclk {

	refclk: mssrefclk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

	};
@@ -190,7 +190,7 @@ 


		clkcfg: clkcfg@20002000 {

			compatible = "microchip,mpfs-clkcfg";

			reg = <0x0 0x20002000 0x0 0x1000>;

			reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;

			clocks = <&refclk>;

			#clock-cells = <1>;

		};
@@ -393,8 +393,8 @@ 
			reg = <0x0 0x20124000 0x0 0x1000>;

			interrupt-parent = <&plic>;

			interrupts = <80>, <81>;

			clocks = <&clkcfg CLK_RTC>;

			clock-names = "rtc";

			clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;

			clock-names = "rtc", "rtcref";

			status = "disabled";

		};
@@ -424,7 +424,7 @@ 
					<0 0 0 3 &pcie_intc 2>,

					<0 0 0 4 &pcie_intc 3>;

			interrupt-map-mask = <0 0 0 7>;

			clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;

			clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;

			clock-names = "fic0", "fic1", "fic3";

			ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;

			msi-parent = <&pcie>;