Commit c0be8f18 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Will Deacon
Browse files

arm64: head: factor out TTBR1 assignment into a macro 



Create a macro load_ttbr1 to avoid having to repeat the same instruction
sequence 3 times in a subsequent patch. No functional change intended.

Signed-off-by: default avatarArd Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20220624150651.1358849-17-ardb@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent a004393f

arch/arm64/include/asm/assembler.h

+13 −4
Original line number Diff line number Diff line
@@ -479,6 +479,18 @@ alternative_endif 
	_cond_extable .Licache_op\@, \fixup

	.endm



/*

 * load_ttbr1 - install @pgtbl as a TTBR1 page table

 * pgtbl preserved

 * tmp1/tmp2 clobbered, either may overlap with pgtbl

 */

	.macro		load_ttbr1, pgtbl, tmp1, tmp2

	phys_to_ttbr	\tmp1, \pgtbl

	offset_ttbr1 	\tmp1, \tmp2

	msr		ttbr1_el1, \tmp1

	isb

	.endm



/*

 * To prevent the possibility of old and new partial table walks being visible

 * in the tlb, switch the ttbr to a zero page when we invalidate the old
@@ -492,10 +504,7 @@ alternative_endif 
	isb

	tlbi	vmalle1

	dsb	nsh

	phys_to_ttbr \tmp, \page_table

	offset_ttbr1 \tmp, \tmp2

	msr	ttbr1_el1, \tmp

	isb

	load_ttbr1 \page_table, \tmp, \tmp2

	.endm



/*

arch/arm64/kernel/head.S

+1 −4
Original line number Diff line number Diff line
@@ -722,12 +722,9 @@ SYM_FUNC_START(__enable_mmu) 
	cmp     x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX

	b.gt    __no_granule_support

	update_early_cpu_boot_status 0, x3, x4

	phys_to_ttbr x1, x1

	phys_to_ttbr x2, x2

	msr	ttbr0_el1, x2			// load TTBR0

	offset_ttbr1 x1, x3

	msr	ttbr1_el1, x1			// load TTBR1

	isb

	load_ttbr1 x1, x1, x3



	set_sctlr_el1	x0