Commit c0b15c25 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
Browse files

arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55 



The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
we apply the work around for r0p0 - r1p0. Unfortunately this
won't be fixed for the future revisions for the CPU. Thus
extend the work around for all versions of A55, to cover
for r2p0 and any future revisions.

Cc: stable@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210203230057.3961239-1-suzuki.poulose@arm.com


[will: Update Kconfig help text]
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 19c329f6

arch/arm64/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -522,7 +522,7 @@ config ARM64_ERRATUM_1024718 
	help

	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.



	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect

	  Affected Cortex-A55 cores (all revisions) could cause incorrect

	  update of the hardware dirty bit when the DBM/AP bits are updated

	  without a break-before-make. The workaround is to disable the usage

	  of hardware DBM locally on the affected cores. CPUs not affected by

arch/arm64/kernel/cpufeature.c

+1 −1
Original line number Diff line number Diff line
@@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void) 
	/* List of CPUs which have broken DBM support. */

	static const struct midr_range cpus[] = {

#ifdef CONFIG_ARM64_ERRATUM_1024718

		MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),

		/* Kryo4xx Silver (rdpe => r1p0) */

		MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),

#endif