Commit c05ffb1f authored by Lang Cheng's avatar Lang Cheng Committed by Jason Gunthorpe
Browse files

RDMA/hns: Move HIP06 related definitions into hns_roce_hw_v1.h 

hns_roce_device.h is not specific to hardware, some definitions are only
used for HIP06, they should be moved into hns_roce_hw_v1.h.

Link: https://lore.kernel.org/r/1612517974-31867-9-git-send-email-liweihang@huawei.com


Signed-off-by: default avatarLang Cheng <chenglang@huawei.com>
Signed-off-by: default avatarWeihang Li <liweihang@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent 86f767e6

drivers/infiniband/hw/hns/hns_roce_device.h

+0 −41
Original line number Diff line number Diff line
@@ -170,44 +170,6 @@ enum hns_roce_event { 
	HNS_ROCE_EVENT_TYPE_FLR			      = 0x15,

};



/* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */

enum {

	HNS_ROCE_LWQCE_QPC_ERROR		= 1,

	HNS_ROCE_LWQCE_MTU_ERROR		= 2,

	HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR	= 3,

	HNS_ROCE_LWQCE_WQE_ADDR_ERROR		= 4,

	HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR	= 5,

	HNS_ROCE_LWQCE_SL_ERROR			= 6,

	HNS_ROCE_LWQCE_PORT_ERROR		= 7,

};



/* Local Access Violation Work Queue Error,SUBTYPE 0x7 */

enum {

	HNS_ROCE_LAVWQE_R_KEY_VIOLATION		= 1,

	HNS_ROCE_LAVWQE_LENGTH_ERROR		= 2,

	HNS_ROCE_LAVWQE_VA_ERROR		= 3,

	HNS_ROCE_LAVWQE_PD_ERROR		= 4,

	HNS_ROCE_LAVWQE_RW_ACC_ERROR		= 5,

	HNS_ROCE_LAVWQE_KEY_STATE_ERROR		= 6,

	HNS_ROCE_LAVWQE_MR_OPERATION_ERROR	= 7,

};



/* DOORBELL overflow subtype */

enum {

	HNS_ROCE_DB_SUBTYPE_SDB_OVF		= 1,

	HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF		= 2,

	HNS_ROCE_DB_SUBTYPE_ODB_OVF		= 3,

	HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF		= 4,

	HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP		= 5,

	HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP		= 6,

};



enum {

	/* RQ&SRQ related operations */

	HNS_ROCE_OPCODE_SEND_DATA_RECEIVE	= 0x06,

	HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE	= 0x07,

};



#define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12



enum {
@@ -260,9 +222,6 @@ enum { 


#define HNS_ROCE_CMD_SUCCESS			1



#define HNS_ROCE_PORT_DOWN			0

#define HNS_ROCE_PORT_UP			1



/* The minimum page size is 4K for hardware */

#define HNS_HW_PAGE_SHIFT			12

#define HNS_HW_PAGE_SIZE			(1 << HNS_HW_PAGE_SHIFT)

drivers/infiniband/hw/hns/hns_roce_hw_v1.h

+43 −0
Original line number Diff line number Diff line
@@ -193,6 +193,49 @@ 
#define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S 0

#define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M GENMASK(4, 0)



/* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */

enum {

	HNS_ROCE_LWQCE_QPC_ERROR = 1,

	HNS_ROCE_LWQCE_MTU_ERROR,

	HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR,

	HNS_ROCE_LWQCE_WQE_ADDR_ERROR,

	HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR,

	HNS_ROCE_LWQCE_SL_ERROR,

	HNS_ROCE_LWQCE_PORT_ERROR,

};



/* Local Access Violation Work Queue Error,SUBTYPE 0x7 */

enum {

	HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1,

	HNS_ROCE_LAVWQE_LENGTH_ERROR,

	HNS_ROCE_LAVWQE_VA_ERROR,

	HNS_ROCE_LAVWQE_PD_ERROR,

	HNS_ROCE_LAVWQE_RW_ACC_ERROR,

	HNS_ROCE_LAVWQE_KEY_STATE_ERROR,

	HNS_ROCE_LAVWQE_MR_OPERATION_ERROR,

};



/* DOORBELL overflow subtype */

enum {

	HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1,

	HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF,

	HNS_ROCE_DB_SUBTYPE_ODB_OVF,

	HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF,

	HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP,

	HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP,

};



enum {

	/* RQ&SRQ related operations */

	HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06,

	HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE,

};



enum {

	HNS_ROCE_PORT_DOWN = 0,

	HNS_ROCE_PORT_UP,

};



struct hns_roce_cq_context {

	__le32 cqc_byte_4;

	__le32 cq_bt_l;