Commit c0474a60 authored by Lu Baolu's avatar Lu Baolu Committed by Joerg Roedel
Browse files

iommu/vt-d: Invalidate PASID cache when root/context entry changed 



When the Intel IOMMU is operating in the scalable mode, some information
from the root and context table may be used to tag entries in the PASID
cache. Software should invalidate the PASID-cache when changing root or
context table entries.

Suggested-by: default avatarAshok Raj <ashok.raj@intel.com>
Fixes: 7373a8cc ("iommu/vt-d: Setup context and enable RID2PASID support")
Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210320025415.641201-4-baolu.lu@linux.intel.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent eea53c58

drivers/iommu/intel/iommu.c

+9 −9
Original line number Diff line number Diff line
@@ -1347,6 +1347,11 @@ static void iommu_set_root_entry(struct intel_iommu *iommu) 
		      readl, (sts & DMA_GSTS_RTPS), sts);



	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);



	iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);

	if (sm_supported(iommu))

		qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0);

	iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);

}



void iommu_flush_write_buffer(struct intel_iommu *iommu)
@@ -2430,6 +2435,10 @@ static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn 
				   (((u16)bus) << 8) | devfn,

				   DMA_CCMD_MASK_NOBIT,

				   DMA_CCMD_DEVICE_INVL);



	if (sm_supported(iommu))

		qi_flush_pasid_cache(iommu, did_old, QI_PC_ALL_PASIDS, 0);



	iommu->flush.flush_iotlb(iommu,

				 did_old,

				 0,
@@ -3278,8 +3287,6 @@ static int __init init_dmars(void) 
		register_pasid_allocator(iommu);

#endif

		iommu_set_root_entry(iommu);

		iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);

		iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);

	}



#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
@@ -3469,12 +3476,7 @@ static int init_iommu_hw(void) 
		}



		iommu_flush_write_buffer(iommu);



		iommu_set_root_entry(iommu);



		iommu->flush.flush_context(iommu, 0, 0, 0,

					   DMA_CCMD_GLOBAL_INVL);

		iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);

		iommu_enable_translation(iommu);

		iommu_disable_protect_mem_regions(iommu);

	}
@@ -3857,8 +3859,6 @@ static int intel_iommu_add(struct dmar_drhd_unit *dmaru) 
		goto disable_iommu;



	iommu_set_root_entry(iommu);

	iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);

	iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);

	iommu_enable_translation(iommu);



	iommu_disable_protect_mem_regions(iommu);

include/linux/intel-iommu.h

+1 −0
Original line number Diff line number Diff line
@@ -378,6 +378,7 @@ enum { 
/* PASID cache invalidation granu */

#define QI_PC_ALL_PASIDS	0

#define QI_PC_PASID_SEL		1

#define QI_PC_GLOBAL		3



#define QI_EIOTLB_ADDR(addr)	((u64)(addr) & VTD_PAGE_MASK)

#define QI_EIOTLB_IH(ih)	(((u64)ih) << 6)