Commit bfed8731 authored by Yong Wu's avatar Yong Wu Committed by Will Deacon
Browse files

iommu/mediatek: Support up to 34bit iova in tlb flush 



If the iova is 34bit, the iova[32][33] is the bit0/1 in the tlb flush
register. Add a new macro for this.

In the macro, since (iova + size - 1) may be end with 0xfff, then the
bit0/1 always is 1, thus add a mask.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarTomasz Figa <tfiga@chromium.org>
Link: https://lore.kernel.org/r/20210111111914.22211-22-yong.wu@mediatek.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent c0b57581

drivers/iommu/mtk_iommu.c

+8 −2
Original line number Diff line number Diff line
@@ -129,6 +129,11 @@ static const struct iommu_ops mtk_iommu_ops; 


static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);



#define MTK_IOMMU_TLB_ADDR(iova) ({					\

	dma_addr_t _addr = iova;					\

	((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\

})



/*

 * In M4U 4GB mode, the physical address is remapped as below:

 *
@@ -213,8 +218,9 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 
		writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,

			       data->base + data->plat_data->inv_sel_reg);



		writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);

		writel_relaxed(iova + size - 1,

		writel_relaxed(MTK_IOMMU_TLB_ADDR(iova),

			       data->base + REG_MMU_INVLD_START_A);

		writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),

			       data->base + REG_MMU_INVLD_END_A);

		writel_relaxed(F_MMU_INV_RANGE,

			       data->base + REG_MMU_INVALIDATE);