Commit bfe3b194 authored Jul 17, 2020 by Athira Rajeev Committed by Michael Ellerman Jul 22, 2020

powerpc/perf: Ignore the BHRB kernel address filtering for P10

Commit bb19af81 ("powerpc/perf: Prevent kernel address leak to
userspace via BHRB buffer") added a check in bhrb_read() to filter
the kernel address from BHRB buffer. This patch modified it to avoid
that check for PowerISA v3.1 based processors, since PowerISA v3.1
allows only MSR[PR]=1 address to be written to BHRB buffer.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1594996707-3727-10-git-send-email-atrajeev@linux.vnet.ibm.com

parent a64e697c

arch/powerpc/perf/core-book3s.c

+4 −1

Original line number	Diff line number	Diff line
		@@ -470,8 +470,11 @@ static void power_pmu_bhrb_read(struct perf_event event, struct cpu_hw_events
		* addresses at this point. Check the privileges before
		* exporting it to userspace (avoid exposure of regions
		* where we could have speculative execution)
		* Incase of ISA v3.1, BHRB will capture only user-space
		* addresses, hence include a check before filtering code
		*/
		if (is_kernel_addr(addr) && perf_allow_kernel(&event->attr) != 0)
		if (!(ppmu->flags & PPMU_ARCH_31) &&
		is_kernel_addr(addr) && perf_allow_kernel(&event->attr) != 0)
		continue;

		/* Branches are read most recent first (ie. mfbhrb 0 is