Commit bfb34ece authored by Md Sadre Alam's avatar Md Sadre Alam Committed by Miquel Raynal
Browse files

mtd: rawnand: qcom: avoid writing to obsolete register 



QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
Avoid writing this register if QPIC version is V2.0 or newer.

Signed-off-by: default avatarMd Sadre Alam <mdalam@codeaurora.org>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1623134916-562-1-git-send-email-mdalam@codeaurora.org
parent f856c4e9

drivers/mtd/nand/raw/qcom_nandc.c

+12 −6
Original line number Diff line number Diff line
@@ -734,6 +734,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i 
{

	struct nand_chip *chip = &host->chip;

	u32 cmd, cfg0, cfg1, ecc_bch_cfg;

	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);



	if (read) {

		if (host->use_ecc)
@@ -762,6 +763,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i 
	nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0);

	nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1);

	nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg);

	if (!nandc->props->qpic_v2)

		nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);

	nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);

	nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);
@@ -1133,6 +1135,7 @@ static void config_nand_page_read(struct nand_chip *chip) 


	write_reg_dma(nandc, NAND_ADDR0, 2, 0);

	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);

	if (!nandc->props->qpic_v2)

		write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);

	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);

	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
@@ -1191,6 +1194,7 @@ static void config_nand_page_write(struct nand_chip *chip) 


	write_reg_dma(nandc, NAND_ADDR0, 2, 0);

	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);

	if (!nandc->props->qpic_v2)

		write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,

			      NAND_BAM_NEXT_SGL);

}
@@ -1248,6 +1252,7 @@ static int nandc_param(struct qcom_nand_host *host) 
					| 2 << WR_RD_BSY_GAP

					| 0 << WIDE_FLASH

					| 1 << DEV0_CFG1_ECC_DISABLE);

	if (!nandc->props->qpic_v2)

		nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);



	/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
@@ -2688,6 +2693,7 @@ static int qcom_nand_attach_chip(struct nand_chip *chip) 
				| ecc_mode << ECC_MODE

				| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;



	if (!nandc->props->qpic_v2)

		host->ecc_buf_cfg = 0x203 << NUM_STEPS;



	host->clrflashstatus = FS_READY_BSY_N;