clk: qcom: gpucc-sm8550: Add support for graphics clock controller (bfae4074) · Commits · EulixOS / Software / Kernel

drivers/clk/qcom/Kconfig

+8 −0

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		@@ -983,6 +983,14 @@ config SM_GPUCC_8450
		Say Y if you want to support graphics controller devices and
		functionality such as 3D graphics.

		config SM_GPUCC_8550
		tristate "SM8550 Graphics Clock Controller"
		select SM_GCC_8550
		help
		Support for the graphics clock controller on SM8550 devices.
		Say Y if you want to support graphics controller devices and
		functionality such as 3D graphics.

		config SM_TCSRCC_8550
		tristate "SM8550 TCSR Clock Controller"
		depends on ARM64 \|\| COMPILE_TEST

drivers/clk/qcom/Makefile

+1 −0

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		@@ -126,6 +126,7 @@ obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
		obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
		obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
		obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
		obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
		obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
		obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
		obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o

drivers/clk/qcom/gpucc-sm8550.c

0 → 100644

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Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
		*/

		#include <linux/clk-provider.h>
		#include <linux/module.h>
		#include <linux/of_device.h>
		#include <linux/regmap.h>

		#include <dt-bindings/clock/qcom,sm8550-gpucc.h>

		#include "clk-alpha-pll.h"
		#include "clk-branch.h"
		#include "clk-rcg.h"
		#include "clk-regmap.h"
		#include "clk-regmap-divider.h"
		#include "common.h"
		#include "gdsc.h"
		#include "reset.h"

		enum {
		DT_BI_TCXO,
		DT_GPLL0_OUT_MAIN,
		DT_GPLL0_OUT_MAIN_DIV,
		};

		enum {
		P_BI_TCXO,
		P_GPLL0_OUT_MAIN,
		P_GPLL0_OUT_MAIN_DIV,
		P_GPU_CC_PLL0_OUT_MAIN,
		P_GPU_CC_PLL1_OUT_MAIN,
		};

		static const struct pll_vco lucid_ole_vco[] = {
		{ 249600000, 2300000000, 0 },
		};

		static const struct alpha_pll_config gpu_cc_pll0_config = {
		/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
		.l = 0x4444000d,
		.alpha = 0x0,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00182261,
		.config_ctl_hi1_val = 0x82aa299c,
		.test_ctl_val = 0x00000000,
		.test_ctl_hi_val = 0x00000003,
		.test_ctl_hi1_val = 0x00009000,
		.test_ctl_hi2_val = 0x00000034,
		.user_ctl_val = 0x00000000,
		.user_ctl_hi_val = 0x00000005,
		};

		static struct clk_alpha_pll gpu_cc_pll0 = {
		.offset = 0x0,
		.vco_table = lucid_ole_vco,
		.num_vco = ARRAY_SIZE(lucid_ole_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
		.clkr = {
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_pll0",
		.parent_data = &(const struct clk_parent_data) {
		.index = DT_BI_TCXO,
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_lucid_evo_ops,
		},
		},
		};

		static const struct alpha_pll_config gpu_cc_pll1_config = {
		/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
		.l = 0x44440016,
		.alpha = 0xeaaa,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00182261,
		.config_ctl_hi1_val = 0x82aa299c,
		.test_ctl_val = 0x00000000,
		.test_ctl_hi_val = 0x00000003,
		.test_ctl_hi1_val = 0x00009000,
		.test_ctl_hi2_val = 0x00000034,
		.user_ctl_val = 0x00000000,
		.user_ctl_hi_val = 0x00000005,
		};

		static struct clk_alpha_pll gpu_cc_pll1 = {
		.offset = 0x1000,
		.vco_table = lucid_ole_vco,
		.num_vco = ARRAY_SIZE(lucid_ole_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
		.clkr = {
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_pll1",
		.parent_data = &(const struct clk_parent_data) {
		.index = DT_BI_TCXO,
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_lucid_evo_ops,
		},
		},
		};

		static const struct parent_map gpu_cc_parent_map_0[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPLL0_OUT_MAIN, 5 },
		{ P_GPLL0_OUT_MAIN_DIV, 6 },
		};

		static const struct clk_parent_data gpu_cc_parent_data_0[] = {
		{ .index = DT_BI_TCXO },
		{ .index = DT_GPLL0_OUT_MAIN },
		{ .index = DT_GPLL0_OUT_MAIN_DIV },
		};

		static const struct parent_map gpu_cc_parent_map_1[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
		{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
		{ P_GPLL0_OUT_MAIN, 5 },
		{ P_GPLL0_OUT_MAIN_DIV, 6 },
		};

		static const struct clk_parent_data gpu_cc_parent_data_1[] = {
		{ .index = DT_BI_TCXO },
		{ .hw = &gpu_cc_pll0.clkr.hw },
		{ .hw = &gpu_cc_pll1.clkr.hw },
		{ .index = DT_GPLL0_OUT_MAIN },
		{ .index = DT_GPLL0_OUT_MAIN_DIV },
		};

		static const struct parent_map gpu_cc_parent_map_2[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
		{ P_GPLL0_OUT_MAIN, 5 },
		{ P_GPLL0_OUT_MAIN_DIV, 6 },
		};

		static const struct clk_parent_data gpu_cc_parent_data_2[] = {
		{ .index = DT_BI_TCXO },
		{ .hw = &gpu_cc_pll1.clkr.hw },
		{ .index = DT_GPLL0_OUT_MAIN },
		{ .index = DT_GPLL0_OUT_MAIN_DIV },
		};

		static const struct parent_map gpu_cc_parent_map_3[] = {
		{ P_BI_TCXO, 0 },
		};

		static const struct clk_parent_data gpu_cc_parent_data_3[] = {
		{ .index = DT_BI_TCXO },
		};

		static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
		F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
		{ }
		};

		static struct clk_rcg2 gpu_cc_ff_clk_src = {
		.cmd_rcgr = 0x9474,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gpu_cc_parent_map_0,
		.freq_tbl = ftbl_gpu_cc_ff_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_ff_clk_src",
		.parent_data = gpu_cc_parent_data_0,
		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
		F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
		{ }
		};

		static struct clk_rcg2 gpu_cc_gmu_clk_src = {
		.cmd_rcgr = 0x9318,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gpu_cc_parent_map_1,
		.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_gmu_clk_src",
		.parent_data = gpu_cc_parent_data_1,
		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
		F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
		F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
		F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
		{ }
		};

		static struct clk_rcg2 gpu_cc_hub_clk_src = {
		.cmd_rcgr = 0x93ec,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gpu_cc_parent_map_2,
		.freq_tbl = ftbl_gpu_cc_hub_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_hub_clk_src",
		.parent_data = gpu_cc_parent_data_2,
		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 gpu_cc_xo_clk_src = {
		.cmd_rcgr = 0x9010,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gpu_cc_parent_map_3,
		.freq_tbl = ftbl_gpu_cc_xo_clk_src,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_xo_clk_src",
		.parent_data = gpu_cc_parent_data_3,
		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_shared_ops,
		},
		};

		static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
		.reg = 0x9054,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_demet_div_clk_src",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_xo_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
		.reg = 0x9050,
		.shift = 0,
		.width = 4,
		.clkr.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_xo_div_clk_src",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_xo_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_regmap_div_ro_ops,
		},
		};

		static struct clk_branch gpu_cc_ahb_clk = {
		.halt_reg = 0x911c,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x911c,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_ahb_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_hub_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_crc_ahb_clk = {
		.halt_reg = 0x9120,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x9120,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_crc_ahb_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_hub_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cx_ff_clk = {
		.halt_reg = 0x914c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x914c,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_cx_ff_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_ff_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cx_gmu_clk = {
		.halt_reg = 0x913c,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x913c,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_cx_gmu_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_gmu_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_aon_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_cxo_clk = {
		.halt_reg = 0x9144,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x9144,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_cxo_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_xo_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_freq_measure_clk = {
		.halt_reg = 0x9008,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x9008,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_freq_measure_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_xo_div_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
		.halt_reg = 0x7000,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x7000,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_hub_aon_clk = {
		.halt_reg = 0x93e8,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x93e8,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_hub_aon_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_hub_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_aon_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_hub_cx_int_clk = {
		.halt_reg = 0x9148,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x9148,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_hub_cx_int_clk",
		.parent_hws = (const struct clk_hw*[]) {
		&gpu_cc_hub_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_aon_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_memnoc_gfx_clk = {
		.halt_reg = 0x9150,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x9150,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_memnoc_gfx_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
		.halt_reg = 0x9288,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x9288,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_mnd1x_0_gfx3d_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
		.halt_reg = 0x928c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x928c,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_mnd1x_1_gfx3d_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_sleep_clk = {
		.halt_reg = 0x9134,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x9134,
		.enable_mask = BIT(0),
		.hw.init = &(const struct clk_init_data) {
		.name = "gpu_cc_sleep_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct gdsc gpu_cc_cx_gdsc = {
		.gdscr = 0x9108,
		.gds_hw_ctrl = 0x953c,
		.en_rest_wait_val = 0x2,
		.en_few_wait_val = 0x2,
		.clk_dis_wait_val = 0xf,
		.pd = {
		.name = "gpu_cc_cx_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		.flags = RETAIN_FF_ENABLE \| VOTABLE,
		};

		static struct gdsc gpu_cc_gx_gdsc = {
		.gdscr = 0x905c,
		.clamp_io_ctrl = 0x9504,
		.en_rest_wait_val = 0x2,
		.en_few_wait_val = 0x2,
		.clk_dis_wait_val = 0xf,
		.pd = {
		.name = "gpu_cc_gx_gdsc",
		.power_on = gdsc_gx_do_nothing_enable,
		},
		.pwrsts = PWRSTS_OFF_ON,
		.flags = CLAMP_IO \| POLL_CFG_GDSCR \| RETAIN_FF_ENABLE,
		};

		static struct clk_regmap *gpu_cc_sm8550_clocks[] = {
		[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
		[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
		[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
		[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
		[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
		[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
		[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
		[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
		[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
		[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
		[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
		[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
		[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
		[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
		[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
		[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
		[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
		[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
		[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
		[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
		[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
		};

		static struct gdsc *gpu_cc_sm8550_gdscs[] = {
		[GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
		[GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
		};

		static const struct qcom_reset_map gpu_cc_sm8550_resets[] = {
		[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
		[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
		[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
		[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
		[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
		[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
		[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
		[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
		};

		static const struct regmap_config gpu_cc_sm8550_regmap_config = {
		.reg_bits = 32,
		.reg_stride = 4,
		.val_bits = 32,
		.max_register = 0x9988,
		.fast_io = true,
		};

		static const struct qcom_cc_desc gpu_cc_sm8550_desc = {
		.config = &gpu_cc_sm8550_regmap_config,
		.clks = gpu_cc_sm8550_clocks,
		.num_clks = ARRAY_SIZE(gpu_cc_sm8550_clocks),
		.resets = gpu_cc_sm8550_resets,
		.num_resets = ARRAY_SIZE(gpu_cc_sm8550_resets),
		.gdscs = gpu_cc_sm8550_gdscs,
		.num_gdscs = ARRAY_SIZE(gpu_cc_sm8550_gdscs),
		};

		static const struct of_device_id gpu_cc_sm8550_match_table[] = {
		{ .compatible = "qcom,sm8550-gpucc" },
		{ }
		};
		MODULE_DEVICE_TABLE(of, gpu_cc_sm8550_match_table);

		static int gpu_cc_sm8550_probe(struct platform_device *pdev)
		{
		struct regmap *regmap;

		regmap = qcom_cc_map(pdev, &gpu_cc_sm8550_desc);
		if (IS_ERR(regmap))
		return PTR_ERR(regmap);

		clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
		clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);

		/*
		* Keep clocks always enabled:
		* gpu_cc_cxo_aon_clk
		* gpu_cc_demet_clk
		*/
		regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0));
		regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0));

		return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap);
		}

		static struct platform_driver gpu_cc_sm8550_driver = {
		.probe = gpu_cc_sm8550_probe,
		.driver = {
		.name = "gpu_cc-sm8550",
		.of_match_table = gpu_cc_sm8550_match_table,
		},
		};

		static int __init gpu_cc_sm8550_init(void)
		{
		return platform_driver_register(&gpu_cc_sm8550_driver);
		}
		subsys_initcall(gpu_cc_sm8550_init);

		static void __exit gpu_cc_sm8550_exit(void)
		{
		platform_driver_unregister(&gpu_cc_sm8550_driver);
		}
		module_exit(gpu_cc_sm8550_exit);

		MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver");
		MODULE_LICENSE("GPL");