Commit bfa78833 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-sc7180: get rid of test clock 



The test clock apparently it's not used by anyone upstream. Remove it.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228185237.3111988-11-dmitry.baryshkov@linaro.org
parent 32bde50f

drivers/clk/qcom/gcc-sc7180.c

+0 −16
Original line number Original line Diff line number Diff line
@@ -23,7 +23,6 @@ 




enum {

enum {

	P_BI_TCXO,

	P_BI_TCXO,

	P_CORE_BI_PLL_TEST_SE,

	P_GPLL0_OUT_EVEN,

	P_GPLL0_OUT_EVEN,

	P_GPLL0_OUT_MAIN,

	P_GPLL0_OUT_MAIN,

	P_GPLL1_OUT_MAIN,

	P_GPLL1_OUT_MAIN,
@@ -162,21 +161,18 @@ static const struct parent_map gcc_parent_map_0[] = { 
	{ P_BI_TCXO, 0 },

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};

};





static const struct clk_parent_data gcc_parent_data_0[] = {

static const struct clk_parent_data gcc_parent_data_0[] = {

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};

};





static const struct clk_parent_data gcc_parent_data_0_ao[] = {

static const struct clk_parent_data gcc_parent_data_0_ao[] = {

	{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },

	{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};

};





static const struct parent_map gcc_parent_map_1[] = {

static const struct parent_map gcc_parent_map_1[] = {
@@ -184,7 +180,6 @@ static const struct parent_map gcc_parent_map_1[] = { 
	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL6_OUT_MAIN, 2 },

	{ P_GPLL6_OUT_MAIN, 2 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};

};





static const struct clk_parent_data gcc_parent_data_1[] = {

static const struct clk_parent_data gcc_parent_data_1[] = {
@@ -192,7 +187,6 @@ static const struct clk_parent_data gcc_parent_data_1[] = { 
	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll6.clkr.hw },

	{ .hw = &gpll6.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};

};





static const struct parent_map gcc_parent_map_2[] = {

static const struct parent_map gcc_parent_map_2[] = {
@@ -201,7 +195,6 @@ static const struct parent_map gcc_parent_map_2[] = { 
	{ P_GPLL1_OUT_MAIN, 4 },

	{ P_GPLL1_OUT_MAIN, 4 },

	{ P_GPLL4_OUT_MAIN, 5 },

	{ P_GPLL4_OUT_MAIN, 5 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};

};





static const struct clk_parent_data gcc_parent_data_2[] = {

static const struct clk_parent_data gcc_parent_data_2[] = {
@@ -210,19 +203,16 @@ static const struct clk_parent_data gcc_parent_data_2[] = { 
	{ .hw = &gpll1.clkr.hw },

	{ .hw = &gpll1.clkr.hw },

	{ .hw = &gpll4.clkr.hw },

	{ .hw = &gpll4.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};

};





static const struct parent_map gcc_parent_map_3[] = {

static const struct parent_map gcc_parent_map_3[] = {

	{ P_BI_TCXO, 0 },

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};

};





static const struct clk_parent_data gcc_parent_data_3[] = {

static const struct clk_parent_data gcc_parent_data_3[] = {

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};

};





static const struct parent_map gcc_parent_map_4[] = {

static const struct parent_map gcc_parent_map_4[] = {
@@ -230,7 +220,6 @@ static const struct parent_map gcc_parent_map_4[] = { 
	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_SLEEP_CLK, 5 },

	{ P_SLEEP_CLK, 5 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};

};





static const struct clk_parent_data gcc_parent_data_4[] = {

static const struct clk_parent_data gcc_parent_data_4[] = {
@@ -238,7 +227,6 @@ static const struct clk_parent_data gcc_parent_data_4[] = { 
	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0.clkr.hw },

	{ .fw_name = "sleep_clk", .name = "sleep_clk" },

	{ .fw_name = "sleep_clk", .name = "sleep_clk" },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};

};





static const struct parent_map gcc_parent_map_5[] = {

static const struct parent_map gcc_parent_map_5[] = {
@@ -246,7 +234,6 @@ static const struct parent_map gcc_parent_map_5[] = { 
	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL7_OUT_MAIN, 3 },

	{ P_GPLL7_OUT_MAIN, 3 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};

};





static const struct clk_parent_data gcc_parent_data_5[] = {

static const struct clk_parent_data gcc_parent_data_5[] = {
@@ -254,21 +241,18 @@ static const struct clk_parent_data gcc_parent_data_5[] = { 
	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll7.clkr.hw },

	{ .hw = &gpll7.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};

};





static const struct parent_map gcc_parent_map_6[] = {

static const struct parent_map gcc_parent_map_6[] = {

	{ P_BI_TCXO, 0 },

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_SLEEP_CLK, 5 },

	{ P_SLEEP_CLK, 5 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};

};





static const struct clk_parent_data gcc_parent_data_6[] = {

static const struct clk_parent_data gcc_parent_data_6[] = {

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0.clkr.hw },

	{ .fw_name = "sleep_clk", .name = "sleep_clk" },

	{ .fw_name = "sleep_clk", .name = "sleep_clk" },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};

};





static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {

static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {