Commit bf9233f9 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 

Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2023-05-17 (ice, MAINTAINERS)

This series contains updates to ice driver and MAINTAINERS file.

Paul refactors PHY to link mode reporting and updates some PHY types to
report more accurate link modes for ice.

Dave removes mutual exclusion policy between LAG and SR-IOV in ice
driver.

Jesse updates link for Intel Wired LAN in the MAINTAINERS file.

* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
  MAINTAINERS: update Intel Ethernet links
  ice: Remove LAG+SRIOV mutual exclusion
  ice: update PHY type to ethtool link mode mapping
  ice: refactor PHY type to ethtool link mode
  ice: update ICE_PHY_TYPE_HIGH_MAX_INDEX
====================

Link: https://lore.kernel.org/r/20230517165530.3179965-1-anthony.l.nguyen@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 643510ce ebdf098a

Documentation/networking/device_drivers/ethernet/intel/ice.rst

+0 −18
Original line number Diff line number Diff line
@@ -84,24 +84,6 @@ Once the VM shuts down, or otherwise releases the VF, the command will 
complete.





Important notes for SR-IOV and Link Aggregation

-----------------------------------------------

Link Aggregation is mutually exclusive with SR-IOV.



- If Link Aggregation is active, SR-IOV VFs cannot be created on the PF.

- If SR-IOV is active, you cannot set up Link Aggregation on the interface.



Bridging and MACVLAN are also affected by this. If you wish to use bridging or

MACVLAN with SR-IOV, you must set up bridging or MACVLAN before enabling

SR-IOV. If you are using bridging or MACVLAN in conjunction with SR-IOV, and

you want to remove the interface from the bridge or MACVLAN, you must follow

these steps:



1. Destroy SR-IOV VFs if they exist

2. Remove the interface from the bridge or MACVLAN

3. Recreate SRIOV VFs as needed





Additional Features and Configurations

======================================

MAINTAINERS

+2 −3
Original line number Diff line number Diff line
@@ -10337,9 +10337,8 @@ M: Jesse Brandeburg <jesse.brandeburg@intel.com> 
M:	Tony Nguyen <anthony.l.nguyen@intel.com>

L:	intel-wired-lan@lists.osuosl.org (moderated for non-subscribers)

S:	Supported

W:	http://www.intel.com/support/feedback.htm

W:	http://e1000.sourceforge.net/

Q:	http://patchwork.ozlabs.org/project/intel-wired-lan/list/

W:	https://www.intel.com/content/www/us/en/support.html

Q:	https://patchwork.ozlabs.org/project/intel-wired-lan/list/

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue.git

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue.git

F:	Documentation/networking/device_drivers/ethernet/intel/

drivers/net/ethernet/intel/ice/ice.h

+1 −19
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#include <linux/pkt_sched.h>

#include <linux/if_bridge.h>

#include <linux/ctype.h>

#include <linux/linkmode.h>

#include <linux/bpf.h>

#include <linux/btf.h>

#include <linux/auxiliary_bus.h>
@@ -813,25 +814,6 @@ static inline bool ice_is_switchdev_running(struct ice_pf *pf) 
	return pf->switchdev.is_running;

}



/**

 * ice_set_sriov_cap - enable SRIOV in PF flags

 * @pf: PF struct

 */

static inline void ice_set_sriov_cap(struct ice_pf *pf)

{

	if (pf->hw.func_caps.common_cap.sr_iov_1_1)

		set_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);

}



/**

 * ice_clear_sriov_cap - disable SRIOV in PF flags

 * @pf: PF struct

 */

static inline void ice_clear_sriov_cap(struct ice_pf *pf)

{

	clear_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);

}



#define ICE_FD_STAT_CTR_BLOCK_COUNT	256

#define ICE_FD_STAT_PF_IDX(base_idx) \

			((base_idx) * ICE_FD_STAT_CTR_BLOCK_COUNT)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

+1 −1
Original line number Diff line number Diff line
@@ -1087,7 +1087,7 @@ struct ice_aqc_get_phy_caps { 
#define ICE_PHY_TYPE_HIGH_100G_CAUI2		BIT_ULL(2)

#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC	BIT_ULL(3)

#define ICE_PHY_TYPE_HIGH_100G_AUI2		BIT_ULL(4)

#define ICE_PHY_TYPE_HIGH_MAX_INDEX		5

#define ICE_PHY_TYPE_HIGH_MAX_INDEX		4



struct ice_aqc_get_phy_caps_data {

	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */

drivers/net/ethernet/intel/ice/ice_ethtool.c

+35 −274
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
/* ethtool support for ice */



#include "ice.h"

#include "ice_ethtool.h"

#include "ice_flow.h"

#include "ice_fltr.h"

#include "ice_lib.h"
@@ -1658,15 +1659,26 @@ ice_mask_min_supported_speeds(struct ice_hw *hw, 
		*phy_types_low &= ~ICE_PHY_TYPE_LOW_MASK_MIN_1G;

}



#define ice_ethtool_advertise_link_mode(aq_link_speed, ethtool_link_mode)    \

	do {								     \

		if (req_speeds & (aq_link_speed) ||			     \

		    (!req_speeds &&					     \

		     (advert_phy_type_lo & phy_type_mask_lo ||		     \

		      advert_phy_type_hi & phy_type_mask_hi)))		     \

			ethtool_link_ksettings_add_link_mode(ks, advertising,\

							ethtool_link_mode);  \

	} while (0)

/**

 * ice_linkmode_set_bit - set link mode bit

 * @phy_to_ethtool: PHY type to ethtool link mode struct to set

 * @ks: ethtool link ksettings struct to fill out

 * @req_speeds: speed requested by user

 * @advert_phy_type: advertised PHY type

 * @phy_type: PHY type

 */

static void

ice_linkmode_set_bit(const struct ice_phy_type_to_ethtool *phy_to_ethtool,

		     struct ethtool_link_ksettings *ks, u32 req_speeds,

		     u64 advert_phy_type, u32 phy_type)

{

	linkmode_set_bit(phy_to_ethtool->link_mode, ks->link_modes.supported);



	if (req_speeds & phy_to_ethtool->aq_link_speed ||

	    (!req_speeds && advert_phy_type & BIT(phy_type)))

		linkmode_set_bit(phy_to_ethtool->link_mode,

				 ks->link_modes.advertising);

}



/**

 * ice_phy_type_to_ethtool - convert the phy_types to ethtool link modes
@@ -1682,11 +1694,10 @@ ice_phy_type_to_ethtool(struct net_device *netdev, 
	struct ice_pf *pf = vsi->back;

	u64 advert_phy_type_lo = 0;

	u64 advert_phy_type_hi = 0;

	u64 phy_type_mask_lo = 0;

	u64 phy_type_mask_hi = 0;

	u64 phy_types_high = 0;

	u64 phy_types_low = 0;

	u16 req_speeds;

	u32 req_speeds;

	u32 i;



	req_speeds = vsi->port_info->phy.link_info.req_speeds;
@@ -1743,272 +1754,22 @@ ice_phy_type_to_ethtool(struct net_device *netdev, 
		advert_phy_type_hi = vsi->port_info->phy.phy_type_high;

	}



	ethtool_link_ksettings_zero_link_mode(ks, supported);

	ethtool_link_ksettings_zero_link_mode(ks, advertising);



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_100BASE_TX |

			   ICE_PHY_TYPE_LOW_100M_SGMII;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     100baseT_Full);



		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100MB,

						100baseT_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_1000BASE_T |

			   ICE_PHY_TYPE_LOW_1G_SGMII;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     1000baseT_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_1000MB,

						1000baseT_Full);

	}

	linkmode_zero(ks->link_modes.supported);

	linkmode_zero(ks->link_modes.advertising);



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_1000BASE_KX;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     1000baseKX_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_1000MB,

						1000baseKX_Full);

	for (i = 0; i < BITS_PER_TYPE(u64); i++) {

		if (phy_types_low & BIT_ULL(i))

			ice_linkmode_set_bit(&phy_type_low_lkup[i], ks,

					     req_speeds, advert_phy_type_lo,

					     i);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_1000BASE_SX |

			   ICE_PHY_TYPE_LOW_1000BASE_LX;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     1000baseX_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_1000MB,

						1000baseX_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_2500BASE_T;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     2500baseT_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_2500MB,

						2500baseT_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_2500BASE_X |

			   ICE_PHY_TYPE_LOW_2500BASE_KX;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     2500baseX_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_2500MB,

						2500baseX_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_5GBASE_T |

			   ICE_PHY_TYPE_LOW_5GBASE_KR;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     5000baseT_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_5GB,

						5000baseT_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_T |

			   ICE_PHY_TYPE_LOW_10G_SFI_DA |

			   ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC |

			   ICE_PHY_TYPE_LOW_10G_SFI_C2C;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     10000baseT_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,

						10000baseT_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_KR_CR1;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     10000baseKR_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,

						10000baseKR_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_SR;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     10000baseSR_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,

						10000baseSR_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_LR;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     10000baseLR_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,

						10000baseLR_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_25GBASE_T |

			   ICE_PHY_TYPE_LOW_25GBASE_CR |

			   ICE_PHY_TYPE_LOW_25GBASE_CR_S |

			   ICE_PHY_TYPE_LOW_25GBASE_CR1 |

			   ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC |

			   ICE_PHY_TYPE_LOW_25G_AUI_C2C;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     25000baseCR_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_25GB,

						25000baseCR_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_25GBASE_SR |

			   ICE_PHY_TYPE_LOW_25GBASE_LR;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     25000baseSR_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_25GB,

						25000baseSR_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_25GBASE_KR |

			   ICE_PHY_TYPE_LOW_25GBASE_KR_S |

			   ICE_PHY_TYPE_LOW_25GBASE_KR1;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     25000baseKR_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_25GB,

						25000baseKR_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_KR4;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     40000baseKR4_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,

						40000baseKR4_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_CR4 |

			   ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC |

			   ICE_PHY_TYPE_LOW_40G_XLAUI;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     40000baseCR4_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,

						40000baseCR4_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_SR4;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     40000baseSR4_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,

						40000baseSR4_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_LR4;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     40000baseLR4_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,

						40000baseLR4_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_50GBASE_CR2 |

			   ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC |

			   ICE_PHY_TYPE_LOW_50G_LAUI2 |

			   ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC |

			   ICE_PHY_TYPE_LOW_50G_AUI2 |

			   ICE_PHY_TYPE_LOW_50GBASE_CP |

			   ICE_PHY_TYPE_LOW_50GBASE_SR |

			   ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC |

			   ICE_PHY_TYPE_LOW_50G_AUI1;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     50000baseCR2_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_50GB,

						50000baseCR2_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_50GBASE_KR2 |

			   ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     50000baseKR2_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_50GB,

						50000baseKR2_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_50GBASE_SR2 |

			   ICE_PHY_TYPE_LOW_50GBASE_LR2 |

			   ICE_PHY_TYPE_LOW_50GBASE_FR |

			   ICE_PHY_TYPE_LOW_50GBASE_LR;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     50000baseSR2_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_50GB,

						50000baseSR2_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_100GBASE_CR4 |

			   ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC |

			   ICE_PHY_TYPE_LOW_100G_CAUI4 |

			   ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC |

			   ICE_PHY_TYPE_LOW_100G_AUI4 |

			   ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4;

	phy_type_mask_hi = ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC |

			   ICE_PHY_TYPE_HIGH_100G_CAUI2 |

			   ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC |

			   ICE_PHY_TYPE_HIGH_100G_AUI2;

	if (phy_types_low & phy_type_mask_lo ||

	    phy_types_high & phy_type_mask_hi) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     100000baseCR4_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,

						100000baseCR4_Full);

	}



	if (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_CP2) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     100000baseCR2_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,

						100000baseCR2_Full);

	}



	if (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_SR4) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     100000baseSR4_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,

						100000baseSR4_Full);

	}



	if (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_SR2) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     100000baseSR2_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,

						100000baseSR2_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_100GBASE_LR4 |

			   ICE_PHY_TYPE_LOW_100GBASE_DR;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     100000baseLR4_ER4_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,

						100000baseLR4_ER4_Full);

	}



	phy_type_mask_lo = ICE_PHY_TYPE_LOW_100GBASE_KR4 |

			   ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4;

	if (phy_types_low & phy_type_mask_lo) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     100000baseKR4_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,

						100000baseKR4_Full);

	}



	if (phy_types_high & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) {

		ethtool_link_ksettings_add_link_mode(ks, supported,

						     100000baseKR2_Full);

		ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,

						100000baseKR2_Full);

	for (i = 0; i < BITS_PER_TYPE(u64); i++) {

		if (phy_types_high & BIT_ULL(i))

			ice_linkmode_set_bit(&phy_type_high_lkup[i], ks,

					     req_speeds, advert_phy_type_hi,

					     i);

	}



}



#define TEST_SET_BITS_TIMEOUT	50