Commit bf83b96f authored by Stephen Warren's avatar Stephen Warren Committed by Thierry Reding
Browse files

clk: tegra: Mark fuse clock as critical 



For a little over a year, U-Boot on Tegra124 has configured the flow
controller to perform automatic RAM re-repair on off->on power
transitions of the CPU rail[1]. This is mandatory for correct operation
of Tegra124. However, RAM re-repair relies on certain clocks, which the
kernel must enable and leave running. The fuse clock is one of those
clocks. Mark this clock as critical so that LP1 power mode (system
suspend) operates correctly.

[1] 3cc7942a4ae5 ARM: tegra: implement RAM repair

Reported-by: default avatarJonathan Hunter <jonathanh@nvidia.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent e42617b8

drivers/clk/tegra/clk-tegra-periph.c

+5 −1
Original line number Diff line number Diff line
@@ -777,7 +777,11 @@ static struct tegra_periph_init_data gate_clks[] = { 
	GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),

	GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),

	GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),

	GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),

	/*

	 * Critical for RAM re-repair operation, which must occur on resume

	 * from LP1 system suspend and as part of CCPLEX cluster switching.

	 */

	GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL),

	GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),

	GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),

	GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),