Commit bf32b8f9 authored by Vidya Sagar's avatar Vidya Sagar Committed by Bjorn Helgaas
Browse files

PCI: Disable MSI for Tegra234 Root Ports 

Tegra234 PCIe Root Ports don't generate MSI interrupts for PME and AER
events. Since PCIe spec (r6.0 sec 6.1.4.3) doesn't support using a mix of
INTx and MSI/MSI-X, MSI needs to be disabled to avoid Root Port service
drivers registering their respective ISRs with MSI interrupt and to let
only INTx be used for all events.

Link: https://lore.kernel.org/r/20220721142052.25971-8-vidyas@nvidia.com


Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent b949e466

drivers/pci/quirks.c

+13 −4
Original line number Diff line number Diff line
@@ -2709,10 +2709,10 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 
			nvenet_msi_disable);



/*

 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,

 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't

 * generate MSI interrupts for PME and AER events instead only INTx interrupts

 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts

 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device

 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI

 * interrupts for PME and AER events; instead only INTx interrupts are

 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts

 * for other events, since PCIe specification doesn't support using a mix of

 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port

 * service drivers registering their respective ISRs for MSIs.
@@ -2760,6 +2760,15 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);



/*

 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing