Commit bf26e0bb authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/mem: Declare __flush_dcache_icache() static 



__flush_dcache_icache() is only used in mem.c.

Move it before the functions that use it and declare it static.

And also fix the name of the parameter in the comment.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/3fa903eb5a10b2bc7d99a8c559ffdaa05452d8e0.1617895813.git.christophe.leroy@csgroup.eu
parent b26e8f27

arch/powerpc/include/asm/cacheflush.h

+0 −1
Original line number Diff line number Diff line
@@ -40,7 +40,6 @@ void flush_icache_user_page(struct vm_area_struct *vma, struct page *page, 
#define flush_icache_user_page flush_icache_user_page



void flush_dcache_icache_page(struct page *page);

void __flush_dcache_icache(void *page);



/**

 * flush_dcache_range(): Write any modified data cache blocks out to memory and

arch/powerpc/mm/cacheflush.c

+30 −30
Original line number Diff line number Diff line
@@ -135,6 +135,36 @@ void flush_dcache_page(struct page *page) 
}

EXPORT_SYMBOL(flush_dcache_page);



/**

 * __flush_dcache_icache(): Flush a particular page from the data cache to RAM.

 * Note: this is necessary because the instruction cache does *not*

 * snoop from the data cache.

 *

 * @p: the address of the page to flush

 */

static void __flush_dcache_icache(void *p)

{

	unsigned long addr = (unsigned long)p;



	if (flush_coherent_icache(addr))

		return;



	clean_dcache_range(addr, addr + PAGE_SIZE);



	/*

	 * We don't flush the icache on 44x. Those have a virtual icache and we

	 * don't have access to the virtual address here (it's not the page

	 * vaddr but where it's mapped in user space). The flushing of the

	 * icache on these is handled elsewhere, when a change in the address

	 * space occurs, before returning to user space.

	 */



	if (mmu_has_feature(MMU_FTR_TYPE_44x))

		return;



	invalidate_icache_range(addr, addr + PAGE_SIZE);

}



static void flush_dcache_icache_hugepage(struct page *page)

{

	int i;
@@ -178,36 +208,6 @@ void flush_dcache_icache_page(struct page *page) 
}

EXPORT_SYMBOL(flush_dcache_icache_page);



/**

 * __flush_dcache_icache(): Flush a particular page from the data cache to RAM.

 * Note: this is necessary because the instruction cache does *not*

 * snoop from the data cache.

 *

 * @page: the address of the page to flush

 */

void __flush_dcache_icache(void *p)

{

	unsigned long addr = (unsigned long)p;



	if (flush_coherent_icache(addr))

		return;



	clean_dcache_range(addr, addr + PAGE_SIZE);



	/*

	 * We don't flush the icache on 44x. Those have a virtual icache and we

	 * don't have access to the virtual address here (it's not the page

	 * vaddr but where it's mapped in user space). The flushing of the

	 * icache on these is handled elsewhere, when a change in the address

	 * space occurs, before returning to user space.

	 */



	if (mmu_has_feature(MMU_FTR_TYPE_44x))

		return;



	invalidate_icache_range(addr, addr + PAGE_SIZE);

}



void clear_user_page(void *page, unsigned long vaddr, struct page *pg)

{

	clear_page(page);