Commit bf198e2e authored by Tim Harvey's avatar Tim Harvey Committed by Shawn Guo
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arm64: dts: imx8mm-venice-gw7902: fix pcie bindings 



Update the pcie bindings to the correct dt bindings:
 pcie_phy:
  - use pcie0_refclk
  - add required clock-names
 pcie:
  - remove pcie_phy clock as it comes from phy driver

Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
Reviewed-by: default avatarFabio Estevam <festevam@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 339c8bea

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts

+4 −3
Original line number Diff line number Diff line
@@ -595,7 +595,8 @@ 
&pcie_phy {

	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;

	fsl,clkreq-unsupported;

	clocks = <&clk IMX8MM_CLK_DUMMY>;

	clocks = <&pcie0_refclk>;

	clock-names = "ref";

	status = "okay";

};
@@ -604,8 +605,8 @@ 
	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,

		 <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

		 <&pcie0_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_bus";

	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,

			  <&clk IMX8MM_CLK_PCIE1_CTRL>;

	assigned-clock-rates = <10000000>, <250000000>;