Commit bef873da authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v5.17-tag1' of... 

Merge tag 'renesas-pinctrl-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.17

  - Add generic support for output impedance,
  - Add drive strength and output impedance support for the RZ/G2L SoC,
  - Miscellaneous fixes and improvements.
parents c09acbc4 7c50a407

Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml

+3 −0
Original line number Diff line number Diff line
@@ -114,6 +114,9 @@ properties: 
    description: enable output on a pin without actively driving it

      (such as enabling an output buffer)



  output-impedance-ohms:

    description: set the output impedance of a pin to at most X ohms



  output-low:

    type: boolean

    description: set the pin to output mode with low level

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+2 −0
Original line number Diff line number Diff line
@@ -73,6 +73,8 @@ additionalProperties: 
        pins: true

        drive-strength:

          enum: [ 2, 4, 8, 12 ]

        output-impedance-ohms:

          enum: [ 33, 50, 66, 100 ]

        power-source:

          enum: [ 1800, 2500, 3300 ]

        slew-rate: true

drivers/pinctrl/pinconf-generic.c

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ static const struct pin_config_item conf_items[] = { 
	PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true),

	PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false),

	PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),

	PCONFDUMP(PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, "output impedance", "ohms", true),

	PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),

	PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),

	PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
@@ -179,6 +180,7 @@ static const struct pinconf_generic_params dt_params[] = { 
	{ "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },

	{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },

	{ "output-high", PIN_CONFIG_OUTPUT, 1, },

	{ "output-impedance-ohms", PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, 0 },

	{ "output-low", PIN_CONFIG_OUTPUT, 0, },

	{ "power-source", PIN_CONFIG_POWER_SOURCE, 0 },

	{ "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },

drivers/pinctrl/renesas/pinctrl-rza1.c

+3 −3
Original line number Diff line number Diff line
@@ -757,9 +757,9 @@ static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio) 
}



/**

 * rza1_gpio_disable_free() - reset a pin

 * rza1_gpio_free() - reset a pin

 *

 * Surprisingly, disable_free a gpio, is equivalent to request it.

 * Surprisingly, freeing a gpio is equivalent to requesting it.

 * Reset pin to port mode, with input buffer disabled. This overwrites all

 * port direction settings applied with set_direction

 *
@@ -875,7 +875,7 @@ static int rza1_dt_node_pin_count(struct device_node *np) 
}



/**

 * rza1_parse_pmx_function() - parse a pin mux sub-node

 * rza1_parse_pinmux_node() - parse a pin mux sub-node

 *

 * @rza1_pctl: RZ/A1 pin controller device

 * @np: of pmx sub-node

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+210 −100
Original line number Diff line number Diff line
@@ -35,20 +35,21 @@ 
#define MUX_FUNC(pinconf)	(((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)



/* PIN capabilities */

#define PIN_CFG_IOLH			BIT(0)

#define PIN_CFG_SR			BIT(1)

#define PIN_CFG_IEN			BIT(2)

#define PIN_CFG_PUPD			BIT(3)

#define PIN_CFG_IOLH_SD0		BIT(4)

#define PIN_CFG_IOLH_SD1		BIT(5)

#define PIN_CFG_IOLH_QSPI		BIT(6)

#define PIN_CFG_IOLH_ETH0		BIT(7)

#define PIN_CFG_IOLH_ETH1		BIT(8)

#define PIN_CFG_FILONOFF		BIT(9)

#define PIN_CFG_FILNUM			BIT(10)

#define PIN_CFG_FILCLKSEL		BIT(11)



#define RZG2L_MPXED_PIN_FUNCS		(PIN_CFG_IOLH | \

#define PIN_CFG_IOLH_A			BIT(0)

#define PIN_CFG_IOLH_B			BIT(1)

#define PIN_CFG_SR			BIT(2)

#define PIN_CFG_IEN			BIT(3)

#define PIN_CFG_PUPD			BIT(4)

#define PIN_CFG_IO_VMC_SD0		BIT(5)

#define PIN_CFG_IO_VMC_SD1		BIT(6)

#define PIN_CFG_IO_VMC_QSPI		BIT(7)

#define PIN_CFG_IO_VMC_ETH0		BIT(8)

#define PIN_CFG_IO_VMC_ETH1		BIT(9)

#define PIN_CFG_FILONOFF		BIT(10)

#define PIN_CFG_FILNUM			BIT(11)

#define PIN_CFG_FILCLKSEL		BIT(12)



#define RZG2L_MPXED_PIN_FUNCS		(PIN_CFG_IOLH_A | \

					 PIN_CFG_SR | \

					 PIN_CFG_PUPD | \

					 PIN_CFG_FILONOFF | \
@@ -77,7 +78,7 @@ 
#define RZG2L_SINGLE_PIN		BIT(31)

#define RZG2L_SINGLE_PIN_PACK(p, b, f)	(RZG2L_SINGLE_PIN | \

					 ((p) << 24) | ((b) << 20) | (f))

#define RZG2L_SINGLE_PIN_GET_PORT(x)	(((x) & GENMASK(30, 24)) >> 24)

#define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x)	(((x) & GENMASK(30, 24)) >> 24)

#define RZG2L_SINGLE_PIN_GET_BIT(x)	(((x) & GENMASK(22, 20)) >> 20)

#define RZG2L_SINGLE_PIN_GET_CFGS(x)	((x) & GENMASK(19, 0))
@@ -86,6 +87,7 @@ 
#define PMC(n)			(0x0200 + 0x10 + (n))

#define PFC(n)			(0x0400 + 0x40 + (n) * 4)

#define PIN(n)			(0x0800 + 0x10 + (n))

#define IOLH(n)			(0x1000 + (n) * 8)

#define IEN(n)			(0x1800 + (n) * 8)

#define PWPR			(0x3014)

#define SD_CH(n)		(0x3000 + (n) * 4)
@@ -101,11 +103,13 @@ 
#define PVDD_MASK		0x01

#define PFC_MASK		0x07

#define IEN_MASK		0x01

#define IOLH_MASK		0x03



#define PM_INPUT		0x1

#define PM_OUTPUT		0x2



#define RZG2L_PIN_ID_TO_PORT(id)	((id) / RZG2L_PINS_PER_PORT)

#define RZG2L_PIN_ID_TO_PORT_OFFSET(id)	(RZG2L_PIN_ID_TO_PORT(id) + 0x10)

#define RZG2L_PIN_ID_TO_PIN(id)		((id) % RZG2L_PINS_PER_PORT)



struct rzg2l_dedicated_configs {
@@ -137,6 +141,9 @@ struct rzg2l_pinctrl { 
	spinlock_t			lock;

};



static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 };

static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };



static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,

				       u8 port, u8 pin, u8 func)

{
@@ -424,6 +431,56 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 
	return ret;

}



static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,

				   u32 cfg, u32 port, u8 bit)

{

	u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);

	u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);

	u32 data;



	if (bit >= pincount || port >= pctrl->data->n_port_pins)

		return -EINVAL;



	data = pctrl->data->port_pin_configs[port];

	if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data))

		return -EINVAL;



	return 0;

}



static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,

				 u8 bit, u32 mask)

{

	void __iomem *addr = pctrl->base + offset;



	/* handle _L/_H for 32-bit register read/write */

	if (bit >= 4) {

		bit -= 4;

		addr += 4;

	}



	return (readl(addr) >> (bit * 8)) & mask;

}



static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,

				 u8 bit, u32 mask, u32 val)

{

	void __iomem *addr = pctrl->base + offset;

	unsigned long flags;

	u32 reg;



	/* handle _L/_H for 32-bit register read/write */

	if (bit >= 4) {

		bit -= 4;

		addr += 4;

	}



	spin_lock_irqsave(&pctrl->lock, flags);

	reg = readl(addr) & ~(mask << (bit * 8));

	writel(reg | (val << (bit * 8)), addr);

	spin_unlock_irqrestore(&pctrl->lock, flags);

}



static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,

				     unsigned int _pin,

				     unsigned long *config)
@@ -435,7 +492,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 
	unsigned int arg = 0;

	unsigned long flags;

	void __iomem *addr;

	u32 port = 0, reg;

	u32 port_offset;

	u32 cfg = 0;

	u8 bit = 0;
@@ -443,36 +500,33 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 
		return -EINVAL;



	if (*pin_data & RZG2L_SINGLE_PIN) {

		port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data);

		port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);

		cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);

		bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);

	} else {

		cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);

		port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);

		bit = RZG2L_PIN_ID_TO_PIN(_pin);



		if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))

			return -EINVAL;

	}



	switch (param) {

	case PIN_CONFIG_INPUT_ENABLE:

		if (!(cfg & PIN_CFG_IEN))

			return -EINVAL;

		spin_lock_irqsave(&pctrl->lock, flags);

		/* handle _L/_H for 32-bit register read/write */

		addr = pctrl->base + IEN(port);

		if (bit >= 4) {

			bit -= 4;

			addr += 4;

		}



		reg = readl(addr) & (IEN_MASK << (bit * 8));

		arg = (reg >> (bit * 8)) & 0x1;

		spin_unlock_irqrestore(&pctrl->lock, flags);

		arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK);

		break;



	case PIN_CONFIG_POWER_SOURCE: {

		u32 pwr_reg = 0x0;



		if (cfg & PIN_CFG_IOLH_SD0)

		if (cfg & PIN_CFG_IO_VMC_SD0)

			pwr_reg = SD_CH(0);

		else if (cfg & PIN_CFG_IOLH_SD1)

		else if (cfg & PIN_CFG_IO_VMC_SD1)

			pwr_reg = SD_CH(1);

		else if (cfg & PIN_CFG_IOLH_QSPI)

		else if (cfg & PIN_CFG_IO_VMC_QSPI)

			pwr_reg = QSPI;

		else

			return -EINVAL;
@@ -484,6 +538,28 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 
		break;

	}



	case PIN_CONFIG_DRIVE_STRENGTH: {

		unsigned int index;



		if (!(cfg & PIN_CFG_IOLH_A))

			return -EINVAL;



		index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);

		arg = iolh_groupa_mA[index];

		break;

	}



	case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {

		unsigned int index;



		if (!(cfg & PIN_CFG_IOLH_B))

			return -EINVAL;



		index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);

		arg = iolh_groupb_oi[index];

		break;

	}



	default:

		return -ENOTSUPP;

	}
@@ -504,7 +580,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 
	enum pin_config_param param;

	unsigned long flags;

	void __iomem *addr;

	u32 port = 0, reg;

	u32 port_offset;

	unsigned int i;

	u32 cfg = 0;

	u8 bit = 0;
@@ -513,9 +589,16 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 
		return -EINVAL;



	if (*pin_data & RZG2L_SINGLE_PIN) {

		port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data);

		port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);

		cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);

		bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);

	} else {

		cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);

		port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);

		bit = RZG2L_PIN_ID_TO_PIN(_pin);



		if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))

			return -EINVAL;

	}



	for (i = 0; i < num_configs; i++) {
@@ -528,17 +611,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 
			if (!(cfg & PIN_CFG_IEN))

				return -EINVAL;



			/* handle _L/_H for 32-bit register read/write */

			addr = pctrl->base + IEN(port);

			if (bit >= 4) {

				bit -= 4;

				addr += 4;

			}



			spin_lock_irqsave(&pctrl->lock, flags);

			reg = readl(addr) & ~(IEN_MASK << (bit * 8));

			writel(reg | (arg << (bit * 8)), addr);

			spin_unlock_irqrestore(&pctrl->lock, flags);

			rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg);

			break;

		}
@@ -549,11 +622,11 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 
			if (mV != 1800 && mV != 3300)

				return -EINVAL;



			if (cfg & PIN_CFG_IOLH_SD0)

			if (cfg & PIN_CFG_IO_VMC_SD0)

				pwr_reg = SD_CH(0);

			else if (cfg & PIN_CFG_IOLH_SD1)

			else if (cfg & PIN_CFG_IO_VMC_SD1)

				pwr_reg = SD_CH(1);

			else if (cfg & PIN_CFG_IOLH_QSPI)

			else if (cfg & PIN_CFG_IO_VMC_QSPI)

				pwr_reg = QSPI;

			else

				return -EINVAL;
@@ -564,6 +637,43 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 
			spin_unlock_irqrestore(&pctrl->lock, flags);

			break;

		}



		case PIN_CONFIG_DRIVE_STRENGTH: {

			unsigned int arg = pinconf_to_config_argument(_configs[i]);

			unsigned int index;



			if (!(cfg & PIN_CFG_IOLH_A))

				return -EINVAL;



			for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) {

				if (arg == iolh_groupa_mA[index])

					break;

			}

			if (index >= ARRAY_SIZE(iolh_groupa_mA))

				return -EINVAL;



			rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);

			break;

		}



		case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {

			unsigned int arg = pinconf_to_config_argument(_configs[i]);

			unsigned int index;



			if (!(cfg & PIN_CFG_IOLH_B))

				return -EINVAL;



			for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) {

				if (arg == iolh_groupb_oi[index])

					break;

			}

			if (index >= ARRAY_SIZE(iolh_groupb_oi))

				return -EINVAL;



			rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);

			break;

		}



		default:

			return -EOPNOTSUPP;

		}
@@ -855,24 +965,24 @@ static const u32 rzg2l_gpio_configs[] = { 
	RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),

	RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),

	RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),

	RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),

	RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),

	RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
@@ -890,75 +1000,75 @@ static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { 
	{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,

	 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },

	{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,

	 (PIN_CFG_SR | PIN_CFG_IOLH | PIN_CFG_IEN)) },

	 (PIN_CFG_SR | PIN_CFG_IOLH_A | PIN_CFG_IEN)) },

	{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN)) },

	 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },

	{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },

	{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },

	{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },

	{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },

	{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },

	{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },

	{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },

	{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },

	{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },

	{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },

	{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },

	{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },

	{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },

	{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD1))},

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },

	{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },

	{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },

	{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },

	{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },

	{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },

	{ "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,

	 (PIN_CFG_IOLH | PIN_CFG_SR  | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR  | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,

	 (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },

	{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH | PIN_CFG_SR)) },

	 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },

	{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },

	{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },

	{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },

	{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },