Loading drivers/gpu/drm/amd/amdkfd/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -35,7 +35,7 @@ amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ kfd_kernel_queue_vi.o kfd_kernel_queue_v9.o \ kfd_packet_manager.o kfd_process_queue_manager.o \ kfd_device_queue_manager.o kfd_device_queue_manager_cik.o \ kfd_device_queue_manager_vi.o \ kfd_device_queue_manager_vi.o kfd_device_queue_manager_v9.o \ kfd_interrupt.o kfd_events.o cik_event_interrupt.o \ kfd_dbgdev.o kfd_dbgmgr.o kfd_crat.o Loading drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +9 −1 Original line number Diff line number Diff line Loading @@ -1386,7 +1386,10 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, void __user *alternate_aperture_base, uint64_t alternate_aperture_size) { bool retval; bool retval = true; if (!dqm->asic_ops.set_cache_memory_policy) return retval; mutex_lock(&dqm->lock); Loading Loading @@ -1655,6 +1658,11 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) case CHIP_POLARIS11: device_queue_manager_init_vi_tonga(&dqm->asic_ops); break; case CHIP_VEGA10: case CHIP_RAVEN: device_queue_manager_init_v9(&dqm->asic_ops); break; default: WARN(1, "Unexpected ASIC family %u", dev->device_info->asic_family); Loading drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +2 −0 Original line number Diff line number Diff line Loading @@ -200,6 +200,8 @@ void device_queue_manager_init_vi( struct device_queue_manager_asic_ops *asic_ops); void device_queue_manager_init_vi_tonga( struct device_queue_manager_asic_ops *asic_ops); void device_queue_manager_init_v9( struct device_queue_manager_asic_ops *asic_ops); void program_sh_mem_settings(struct device_queue_manager *dqm, struct qcm_process_device *qpd); unsigned int get_queues_num(struct device_queue_manager *dqm); Loading drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c 0 → 100644 +84 −0 Original line number Diff line number Diff line /* * Copyright 2016-2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "kfd_device_queue_manager.h" #include "vega10_enum.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" #include "sdma0/sdma0_4_0_sh_mask.h" static int update_qpd_v9(struct device_queue_manager *dqm, struct qcm_process_device *qpd); static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q, struct qcm_process_device *qpd); void device_queue_manager_init_v9( struct device_queue_manager_asic_ops *asic_ops) { asic_ops->update_qpd = update_qpd_v9; asic_ops->init_sdma_vm = init_sdma_vm_v9; } static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd) { uint32_t shared_base = pdd->lds_base >> 48; uint32_t private_base = pdd->scratch_base >> 48; return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) | private_base; } static int update_qpd_v9(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { struct kfd_process_device *pdd; pdd = qpd_to_pdd(qpd); /* check if sh_mem_config register already configured */ if (qpd->sh_mem_config == 0) { qpd->sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; if (vega10_noretry && !dqm->dev->device_info->needs_iommu_device) qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; qpd->sh_mem_ape1_limit = 0; qpd->sh_mem_ape1_base = 0; } qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases); return 0; } static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q, struct qcm_process_device *qpd) { /* Not needed on SDMAv4 any more */ q->properties.sdma_vm_addr = 0; } drivers/gpu/drm/amd/amdkfd/kfd_module.c +5 −0 Original line number Diff line number Diff line Loading @@ -83,6 +83,11 @@ module_param(ignore_crat, int, 0444); MODULE_PARM_DESC(ignore_crat, "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); int vega10_noretry; module_param_named(noretry, vega10_noretry, int, 0644); MODULE_PARM_DESC(noretry, "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)"); static int amdkfd_init_completed; int kgd2kfd_init(unsigned int interface_version, Loading Loading
drivers/gpu/drm/amd/amdkfd/Makefile +1 −1 Original line number Diff line number Diff line Loading @@ -35,7 +35,7 @@ amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ kfd_kernel_queue_vi.o kfd_kernel_queue_v9.o \ kfd_packet_manager.o kfd_process_queue_manager.o \ kfd_device_queue_manager.o kfd_device_queue_manager_cik.o \ kfd_device_queue_manager_vi.o \ kfd_device_queue_manager_vi.o kfd_device_queue_manager_v9.o \ kfd_interrupt.o kfd_events.o cik_event_interrupt.o \ kfd_dbgdev.o kfd_dbgmgr.o kfd_crat.o Loading
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +9 −1 Original line number Diff line number Diff line Loading @@ -1386,7 +1386,10 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, void __user *alternate_aperture_base, uint64_t alternate_aperture_size) { bool retval; bool retval = true; if (!dqm->asic_ops.set_cache_memory_policy) return retval; mutex_lock(&dqm->lock); Loading Loading @@ -1655,6 +1658,11 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) case CHIP_POLARIS11: device_queue_manager_init_vi_tonga(&dqm->asic_ops); break; case CHIP_VEGA10: case CHIP_RAVEN: device_queue_manager_init_v9(&dqm->asic_ops); break; default: WARN(1, "Unexpected ASIC family %u", dev->device_info->asic_family); Loading
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +2 −0 Original line number Diff line number Diff line Loading @@ -200,6 +200,8 @@ void device_queue_manager_init_vi( struct device_queue_manager_asic_ops *asic_ops); void device_queue_manager_init_vi_tonga( struct device_queue_manager_asic_ops *asic_ops); void device_queue_manager_init_v9( struct device_queue_manager_asic_ops *asic_ops); void program_sh_mem_settings(struct device_queue_manager *dqm, struct qcm_process_device *qpd); unsigned int get_queues_num(struct device_queue_manager *dqm); Loading
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c 0 → 100644 +84 −0 Original line number Diff line number Diff line /* * Copyright 2016-2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "kfd_device_queue_manager.h" #include "vega10_enum.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" #include "sdma0/sdma0_4_0_sh_mask.h" static int update_qpd_v9(struct device_queue_manager *dqm, struct qcm_process_device *qpd); static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q, struct qcm_process_device *qpd); void device_queue_manager_init_v9( struct device_queue_manager_asic_ops *asic_ops) { asic_ops->update_qpd = update_qpd_v9; asic_ops->init_sdma_vm = init_sdma_vm_v9; } static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd) { uint32_t shared_base = pdd->lds_base >> 48; uint32_t private_base = pdd->scratch_base >> 48; return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) | private_base; } static int update_qpd_v9(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { struct kfd_process_device *pdd; pdd = qpd_to_pdd(qpd); /* check if sh_mem_config register already configured */ if (qpd->sh_mem_config == 0) { qpd->sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; if (vega10_noretry && !dqm->dev->device_info->needs_iommu_device) qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; qpd->sh_mem_ape1_limit = 0; qpd->sh_mem_ape1_base = 0; } qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases); return 0; } static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q, struct qcm_process_device *qpd) { /* Not needed on SDMAv4 any more */ q->properties.sdma_vm_addr = 0; }
drivers/gpu/drm/amd/amdkfd/kfd_module.c +5 −0 Original line number Diff line number Diff line Loading @@ -83,6 +83,11 @@ module_param(ignore_crat, int, 0444); MODULE_PARM_DESC(ignore_crat, "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); int vega10_noretry; module_param_named(noretry, vega10_noretry, int, 0644); MODULE_PARM_DESC(noretry, "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)"); static int amdkfd_init_completed; int kgd2kfd_init(unsigned int interface_version, Loading