Commit beb47f19 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd
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clk: mediatek: mt8167: Convert to mtk_clk_simple_{probe,remove}() 



Convert topckgen and infracfg clock drivers to use the common
mtk_clk_simple_probe() mechanism and change this from the old
"static" CLK_OF_DECLARE to be a platform driver, allowing it
to eventually be built as a module.

Thanks to the conversion, more error handling was added to the clocks
registration.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-19-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent b4bd678f

drivers/clk/mediatek/clk-mt8167-aud.c

+17 −14
Original line number Diff line number Diff line
@@ -48,19 +48,22 @@ static const struct mtk_gate aud_clks[] = { 
	GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),

};



static void __init mtk_audsys_init(struct device_node *node)

{

	struct clk_hw_onecell_data *clk_data;

	int r;



	clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);



	mtk_clk_register_gates(NULL, node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);

static const struct mtk_clk_desc aud_desc = {

	.clks = aud_clks,

	.num_clks = ARRAY_SIZE(aud_clks),

};



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);

static const struct of_device_id of_match_clk_mt8167_audsys[] = {

	{ .compatible = "mediatek,mt8167-audsys", .data = &aud_desc },

	{ /* sentinel */ }

};



}

CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8167-audsys", mtk_audsys_init);
 
static struct platform_driver clk_mt8167_audsys_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt8167-audsys",

		.of_match_table = of_match_clk_mt8167_audsys,

	},

};

module_platform_driver(clk_mt8167_audsys_drv);

drivers/clk/mediatek/clk-mt8167-img.c

+17 −15
Original line number Diff line number Diff line
@@ -41,20 +41,22 @@ static const struct mtk_gate img_clks[] = { 
	GATE_IMG(CLK_IMG_VENC, "img_venc", "smi_mm", 9),

};



static void __init mtk_imgsys_init(struct device_node *node)

{

	struct clk_hw_onecell_data *clk_data;

	int r;



	clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);



	mtk_clk_register_gates(NULL, node, img_clks, ARRAY_SIZE(img_clks), clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

static const struct mtk_clk_desc img_desc = {

	.clks = img_clks,

	.num_clks = ARRAY_SIZE(img_clks),

};



	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);

static const struct of_device_id of_match_clk_mt8167_imgsys[] = {

	{ .compatible = "mediatek,mt8167-imgsys", .data = &img_desc },

	{ /* sentinel */ }

};



}

CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8167-imgsys", mtk_imgsys_init);
 
static struct platform_driver clk_mt8167_imgsys_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt8167-imgsys",

		.of_match_table = of_match_clk_mt8167_imgsys,

	},

};

module_platform_driver(clk_mt8167_imgsys_drv);

drivers/clk/mediatek/clk-mt8167-mfgcfg.c

+17 −15
Original line number Diff line number Diff line
@@ -39,20 +39,22 @@ static const struct mtk_gate mfg_clks[] = { 
	GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3),

};



static void __init mtk_mfgcfg_init(struct device_node *node)

{

	struct clk_hw_onecell_data *clk_data;

	int r;



	clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);



	mtk_clk_register_gates(NULL, node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

static const struct mtk_clk_desc mfg_desc = {

	.clks = mfg_clks,

	.num_clks = ARRAY_SIZE(mfg_clks),

};



	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);

static const struct of_device_id of_match_clk_mt8167_mfgcfg[] = {

	{ .compatible = "mediatek,mt8167-mfgcfg", .data = &mfg_desc },

	{ /* sentinel */ }

};



}

CLK_OF_DECLARE(mtk_mfgcfg, "mediatek,mt8167-mfgcfg", mtk_mfgcfg_init);
 
static struct platform_driver clk_mt8167_mfgcfg_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt8167-mfgcfg",

		.of_match_table = of_match_clk_mt8167_mfgcfg,

	},

};

module_platform_driver(clk_mt8167_mfgcfg_drv);

drivers/clk/mediatek/clk-mt8167-vdec.c

+17 −16
Original line number Diff line number Diff line
@@ -54,21 +54,22 @@ static const struct mtk_gate vdec_clks[] = { 
	GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0),

};



static void __init mtk_vdecsys_init(struct device_node *node)

{

	struct clk_hw_onecell_data *clk_data;

	int r;



	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);



	mtk_clk_register_gates(NULL, node, vdec_clks, ARRAY_SIZE(vdec_clks),

			       clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

static const struct mtk_clk_desc vdec_desc = {

	.clks = vdec_clks,

	.num_clks = ARRAY_SIZE(vdec_clks),

};



	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);

static const struct of_device_id of_match_clk_mt8167_vdec[] = {

	{ .compatible = "mediatek,mt8167-vdecsys", .data = &vdec_desc },

	{ /* sentinel */ }

};



}

CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8167-vdecsys", mtk_vdecsys_init);
 
static struct platform_driver clk_mt8167_vdec_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt8167-vdecsys",

		.of_match_table = of_match_clk_mt8167_vdec,

	},

};

module_platform_driver(clk_mt8167_vdec_drv);

drivers/clk/mediatek/clk-mt8167.c

+33 −53
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/of_address.h>

#include <linux/slab.h>

#include <linux/mfd/syscon.h>

#include <linux/platform_device.h>



#include "clk-gate.h"

#include "clk-mtk.h"
@@ -857,59 +858,38 @@ static const struct mtk_gate top_clks[] = { 
	GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),

};



static void __init mtk_topckgen_init(struct device_node *node)

{

	struct clk_hw_onecell_data *clk_data;

	int r;

	void __iomem *base;



	base = of_iomap(node, 0);

	if (!base) {

		pr_err("%s(): ioremap failed\n", __func__);

		return;

	}



	clk_data = mtk_alloc_clk_data(MT8167_CLK_TOP_NR_CLK);



	mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),

				    clk_data);

	mtk_clk_register_gates(NULL, node, top_clks, ARRAY_SIZE(top_clks), clk_data);



	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);

	mtk_clk_register_composites(NULL, top_muxes,

				    ARRAY_SIZE(top_muxes), base,

				    &mt8167_clk_lock, clk_data);

	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),

				base, &mt8167_clk_lock, clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);

}

CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init);



static void __init mtk_infracfg_init(struct device_node *node)

{

	struct clk_hw_onecell_data *clk_data;

	int r;

	void __iomem *base;



	base = of_iomap(node, 0);

	if (!base) {

		pr_err("%s(): ioremap failed\n", __func__);

		return;

	}

static const struct mtk_clk_desc topck_desc = {

	.clks = top_clks,

	.num_clks = ARRAY_SIZE(top_clks),

	.fixed_clks = fixed_clks,

	.num_fixed_clks = ARRAY_SIZE(fixed_clks),

	.factor_clks = top_divs,

	.num_factor_clks = ARRAY_SIZE(top_divs),

	.composite_clks = top_muxes,

	.num_composite_clks = ARRAY_SIZE(top_muxes),

	.divider_clks = top_adj_divs,

	.num_divider_clks = ARRAY_SIZE(top_adj_divs),

	.clk_lock = &mt8167_clk_lock,

};



	clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);

static const struct mtk_clk_desc infra_desc = {

	.composite_clks = ifr_muxes,

	.num_composite_clks = ARRAY_SIZE(ifr_muxes),

	.clk_lock = &mt8167_clk_lock,

};



	mtk_clk_register_composites(NULL, ifr_muxes,

				    ARRAY_SIZE(ifr_muxes), base,

				    &mt8167_clk_lock, clk_data);

static const struct of_device_id of_match_clk_mt8167[] = {

	{ .compatible = "mediatek,mt8167-topckgen", .data = &topck_desc },

	{ .compatible = "mediatek,mt8167-infracfg", .data = &infra_desc },

	{ /* sentinel */ }

};



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);

}

CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init);
 
static struct platform_driver clk_mt8167_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt8167",

		.of_match_table = of_match_clk_mt8167,

	},

};

module_platform_driver(clk_mt8167_drv);