Commit beb2db9b authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update goldmont mapfile.csv 

Align end of file whitespace with what is generated by:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py



Modify mapfile.csv to have a missing goldmont cpuid.
Event json remains at v13, there are no goldmont metrics.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20220727220832.2865794-9-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 3c9c3157

tools/perf/pmu-events/arch/x86/goldmont/pipeline.json

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Original line number Diff line number Diff line
@@ -354,7 +354,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0xC3",

        "EventName": "MACHINE_CLEARS.SMC",

        "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification.  Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors.",

        "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification.  Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.",

        "SampleAfterValue": "200003",

        "UMask": "0x1"

    },

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ GenuineIntel-6-56,v23,broadwellde,core 
GenuineIntel-6-4F,v19,broadwellx,core

GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core

GenuineIntel-6-96,v1.03,elkhartlake,core

GenuineIntel-6-5C,v8,goldmont,core

GenuineIntel-6-5[CF],v13,goldmont,core

GenuineIntel-6-7A,v1,goldmontplus,core

GenuineIntel-6-3C,v24,haswell,core

GenuineIntel-6-45,v24,haswell,core

tools/perf/pmu-events/arch/x86/goldmont/memory.json

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Contains only whitespace changes.

tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json

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Contains only whitespace changes.

tools/perf/pmu-events/arch/x86/goldmont/cache.json

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Contains only whitespace changes.

tools/perf/pmu-events/arch/x86/goldmont/floating-point.json

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Contains only whitespace changes.

tools/perf/pmu-events/arch/x86/goldmont/frontend.json

+1 −1

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Contains only whitespace changes.