Commit bea307c1 authored by Wolfram Sang's avatar Wolfram Sang Committed by Thierry Reding
Browse files

pwm: img: Test clock rate to avoid division by 0 



The clk API may return 0 on clk_get_rate(), so we should check the
result before using it as a divisor.

Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent 92e963f5

drivers/pwm/pwm-img.c

+5 −0
Original line number Diff line number Diff line
@@ -237,6 +237,11 @@ static int img_pwm_probe(struct platform_device *pdev) 
	}



	clk_rate = clk_get_rate(pwm->pwm_clk);

	if (!clk_rate) {

		dev_err(&pdev->dev, "pwm clock has no frequency\n");

		ret = -EINVAL;

		goto disable_pwmclk;

	}



	/* The maximum input clock divider is 512 */

	val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;