Commit be968269 authored Apr 05, 2021 by Suzuki K Poulose Committed by Mathieu Poirier Apr 05, 2021

arm64: Add support for trace synchronization barrier



tsb csync synchronizes the trace operation of instructions.
The instruction is a nop when FEAT_TRF is not implemented.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210405164307.1720226-4-suzuki.poulose@arm.com


Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

parent 7dde5176

arch/arm64/include/asm/barrier.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -23,6 +23,7 @@
		#define dsb(opt) asm volatile("dsb " #opt : : : "memory")

		#define psb_csync() asm volatile("hint #17" : : : "memory")
		#define tsb_csync() asm volatile("hint #18" : : : "memory")
		#define csdb() asm volatile("hint #20" : : : "memory")

		#define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \