Commit be697aa3 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: move queue_bitmap to an independent structure (v3) 



To allocate independent queue_bitmap for each XCD,
then the old bitmap policy can be continued to use
with a clear logic.

Use mec_bitmap[0] as default for all non-GC 9.4.3 IPs.

v2: squash commits to avoid breaking the build
v3: unify naming style

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 277bd337

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+1 −1
Original line number Diff line number Diff line
@@ -162,7 +162,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 
		 * clear

		 */

		bitmap_complement(gpu_resources.cp_queue_bitmap,

				  adev->gfx.mec.queue_bitmap,

				  adev->gfx.mec_bitmap[0].queue_bitmap,

				  KGD_MAX_QUEUES);



		/* According to linux/bitmap.h we shouldn't use bitmap_clear if

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

+1 −1
Original line number Diff line number Diff line
@@ -778,7 +778,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, 
	 * Iterate through the shader engines and arrays of the device

	 * to get number of waves in flight

	 */

	bitmap_complement(cp_queue_bitmap, adev->gfx.mec.queue_bitmap,

	bitmap_complement(cp_queue_bitmap, adev->gfx.mec_bitmap[0].queue_bitmap,

			  KGD_MAX_QUEUES);

	max_queue_cnt = adev->gfx.mec.num_pipe_per_mec *

			adev->gfx.mec.num_queue_per_pipe;

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+25 −16
Original line number Diff line number Diff line
@@ -63,10 +63,10 @@ void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 
}



bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,

				     int mec, int pipe, int queue)

				     int xcc_id, int mec, int pipe, int queue)

{

	return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),

			adev->gfx.mec.queue_bitmap);

			adev->gfx.mec_bitmap[xcc_id].queue_bitmap);

}



int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
@@ -204,29 +204,38 @@ bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 


void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)

{

	int i, queue, pipe;

	int i, j, queue, pipe;

	bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);

	int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *

				     adev->gfx.mec.num_queue_per_pipe,

				     adev->gfx.num_compute_rings);

	int num_xcd = (adev->gfx.num_xcd > 1) ? adev->gfx.num_xcd : 1;



	if (multipipe_policy) {

		/* policy: make queues evenly cross all pipes on MEC1 only */

		/* policy: make queues evenly cross all pipes on MEC1 only

		 * for multiple xcc, just use the original policy for simplicity */

		for (j = 0; j < num_xcd; j++) {

			for (i = 0; i < max_queues_per_mec; i++) {

				pipe = i % adev->gfx.mec.num_pipe_per_mec;

				queue = (i / adev->gfx.mec.num_pipe_per_mec) %

					 adev->gfx.mec.num_queue_per_pipe;



				set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,

					adev->gfx.mec.queue_bitmap);

					adev->gfx.mec_bitmap[j].queue_bitmap);

			}

		}

	} else {

		/* policy: amdgpu owns all queues in the given pipe */

		for (j = 0; j < num_xcd; j++) {

			for (i = 0; i < max_queues_per_mec; ++i)

			set_bit(i, adev->gfx.mec.queue_bitmap);

				set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);

		}

	}



	dev_dbg(adev->dev, "mec queue bitmap weight=%d\n", bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));

	for (j = 0; j < num_xcd; j++) {

		dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",

			bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));

	}

}



void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
@@ -268,7 +277,7 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, 
		    * adev->gfx.mec.num_queue_per_pipe;



	while (--queue_bit >= 0) {

		if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))

		if (test_bit(queue_bit, adev->gfx.mec_bitmap[0].queue_bitmap))

			continue;



		amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
@@ -516,7 +525,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) 
		return -EINVAL;



	for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {

		if (!test_bit(i, adev->gfx.mec.queue_bitmap))

		if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap))

			continue;



		/* This situation may be hit in the future if a new HW

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+5 −2
Original line number Diff line number Diff line
@@ -76,7 +76,9 @@ struct amdgpu_mec { 
	u32 num_pipe_per_mec;

	u32 num_queue_per_pipe;

	void			*mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];

};



struct amdgpu_mec_bitmap {

	/* These are the resources for which amdgpu takes ownership */

	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);

};
@@ -296,6 +298,7 @@ struct amdgpu_gfx { 
	struct amdgpu_ce		ce;

	struct amdgpu_me		me;

	struct amdgpu_mec		mec;

	struct amdgpu_mec_bitmap	mec_bitmap[AMDGPU_MAX_GC_INSTANCES];

	struct amdgpu_kiq		kiq[AMDGPU_MAX_GC_INSTANCES];

	struct amdgpu_imu		imu;

	bool				rs64_enable; /* firmware format */
@@ -425,8 +428,8 @@ int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 
				int pipe, int queue);

void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,

				 int *mec, int *pipe, int *queue);

bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,

				     int pipe, int queue);

bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int inst,

				     int mec, int pipe, int queue);

bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,

					       struct amdgpu_ring *ring);

bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+3 −3
Original line number Diff line number Diff line
@@ -4219,7 +4219,7 @@ static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 


	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;



	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);

	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);



	/* take ownership of the relevant compute queues */

	amdgpu_gfx_compute_queue_acquire(adev);
@@ -4614,8 +4614,8 @@ static int gfx_v10_0_sw_init(void *handle) 
	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {

		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {

			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {

				if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,

								     j))

				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,

								     k, j))

					continue;



				r = gfx_v10_0_compute_ring_init(adev, ring_id,